[SOLVED] DC offset remova and phase issues

[rawbus]

DC offset removal and phase issues

The current filter I use is from the Xilinx app note on dc offset removal. However, it adds a noticeable phase shift to my signal of 9 degrees at the highest frequency, and around 40 degrees at the lowest. I am comparing this signal with a square wave and the phase is very important. I am sampling around 100 MHz and the signal is anywhere from 10 to 100 KHz. The square wave is the same frequency and is generated internally. The dc offset is not a constant.

A variable tap shift seems too expensive resource wise. Is there another good way to filter the signal?

 

[dave9000]

Re: DC offset removal and phase issues

That dc removal method is comparable to a first order analog filter.
Having a 40 degree phase shift means that you are very close to the time constant of the filter.
A simple solution is just to lower the corner frequency - this probably means you have to use more bits in the registers.
Another solution may be an higher order IIR filter - you need some DSP background for this.

By the way: you said you are "comparing" the signal to an internal square wave of the same frequency.
If you are going to do a synchronous demodulation the offset automagically disappears!

 

[rawbus]

Re: DC offset removal and phase issues

Ah yes, more bits. I suppose I should have tried that earlier. I was going between 8 and 12 and didn't notice much of a difference but 20 seems to fix it. Thanks.