DC , Help instantiating Asics Librarys Full Adder

[nkef]

I am using Design Compiler, width tsmc 0.13 Asic library.
The tsmc library provides full adder cell but Design Compiler is not using it.
I instantiated a full adder using the component instantiation as descripted in Designware User Guide.

library IEEE, GTECH;
use IEEE.std_logic_1164.all;
use GTECH.GTECH_components.all;
entity GT_add_abc_inst is
port(in1, in2, cin : in std_logic;
sum, cout : out std_logic);
end GT_add_abc_inst;
architecture sim of GT_add_abc_inst is
begin
U1 : GTECH_ADD_ABC
port map(A => in1, B => in2,
C => cin,
S => sum, COUT => cout);
end sim;

Dc compiled this full adder with primitive cells
How i can instruct DC to use the full adder cell from Asic Library ?

many thanks
nkef

 

[jackson_peng]

may be you forgot to include the DesignWare Library into your DC setup file

 

[xuanzhu]

you can use the common "+" statement to indicate it is a plus operation, and use according synopsys directive statement in your VHDL comment, then DC will call the DesignWare library cell to do it

 

[nkef]

The Cell from the DesignWare library is instantiated properly after the elaborate command, but after the compile, this cell is replaced with primitives instead of the full adder cell from the asic library.