DC gain requiremet of a Pipelined ADC

[musclesinwood]

Hi,

How do we determine DC gain requirement for a pipelined ADC. I was reading on some papers that it depends on the resolution of the converter. According to the equation

A > 2^N
Where A is the DC gain and N is the resolution of the converter. So , for a 8-bit ADC, minimum required DC gain is 48.16dB according to above euation.

Is it correct way of estimating gain ?

Regards

 

[egni]

Hello,
Your formular is correct but beware: you dont need a gain greater than that you need this GAIN EXACTLY !
A=2^N

Why:
The input range of a pipelined ADC is seperated in different regions (two in case of a simple 1 bit stage or 2^N generally) . Dependent in which region the input is located the first bits of the output code are created. For the next stage this region should spread again over the whole input range (to use the same references of even the same hardware in case of a cyclic ADC). Therefore you need a gain of 2^N (and the according shifting). But you don't wont that input voltages could end up out of the FSR of the ADC. This would happen if you have a gain greater than the one stated. (The same might happen with comparator offset, why redundancy is introduced as the 1.5 bit stage)

The question which is relevant now is how exact your gain must be. This also depends on the resolution, given the allowed error in stage i :
E_i = 1/(N * 2^(N-i))
Which is what you get when you derive from a mathematical perspective.

What you find more commonly as a design rule is
E_i=1/(2^(N-i+2))

G_i = G_ideal*(1 ± E_i)

I hoped that helped! If you need the derivations let me know.

best regards,