DC/DC buck converter power efficiency (voltage mode)

[naeim29]

I'm designing a circuit of DC/DC synchronous buck converter for low power application(voltage mode) in 65nm by Cadence tools,I finished the circuit design and it is able to step down 1.1 V to 400 mV(Reference voltage),but its power efficiency is not good(around 35%)I read so many papers to find how i can optimize the power efficiency and I did so many changes for example sizing of switch transistors,changing frequency,changing driver structure...but still its power efficiency is too low!!!in one paper i found that if difference between input voltage and reference voltage is high the efficiency will reduce but I'm not sure how much it will reduce!I will be so appreciated if someone can help me to how I can increase efficiency!thank you so much!
here is my results so far:

Average Input Current : 103.7 uA
Input Voltage: 1.1 v
Average Output Voltage: 399.8 mv
Average Output Current: 99.9 uA
Switching Frequency: 5 MHz
Settling time: 20 usec
voltage ripple: 3.97 mv (0.99%)
current ripple(peak to peak): 993.4 nA (0.99%)
Power efficiency ([Pout/Pin]%): 35%

 

[RCinFLA]

If you designed the circuit in simulation then you should know where the losses are.

With such a low input and output voltage any voltage drops will take out a lot of efficiency. Also for 100 uA output you are likely eating up a lot in gate drive at 5 Mhz switching. How much are you consuming for vref generation and feedback sense amp.

 

[vimalkhanna]

Can you trace out the schematic diagram to enable determination of losses in power owing to
ref.voltage bias /conversion ,switching and determine the OFF times reduction.
This will improve your efficiency .

 

[atripathi]

You mentioned that you are using synchronous buck converter, in that case cross conduction/RDS on of MOS would be major cause of power loss, you may want to check those.