DC/DC buck converter:Noise ripple output voltage --where's the best method to probe?

[alimjoco]

If the output voltage of a DC/DC converter has 2 filter caps, 22u and 47u..22u connected to the inductor while the 47 connected to the output(22u and 47 u are in parallel connection). where is the best practise to probe the AC output ripple? will I expect the same results if I probe the caps with respect to ground? or I should proble the Vout load with respect to ground?

 

[Miguel Gaspar]

Well, what are you are saying is a bad practice. You never must put capacitors in parallel. A good practice is use only one capacitor with low ESR.
And the frequency cut off must be at least one decade below the switching frequency of comutation.

 

[alimjoco]

I think that the total capacitor value in parallel is well calculated and taken account the required specification of the Vripple, maximum load step and also loop compensation gain. However calculated value yields as 55uF at least, that's why a parallel 22u and 47u was used.

 

[dick_freebird]

Paralleling smaller values is a good way to bring down net
ESR and ESL. You mention no decent low value, low ESR
caps. So I would expect a lot of HF edge noise via the
inductor interwinding capacitance. I've seen people say
you shouldn't parallel caps but their reasoning, I have found
lacking. Our DC-DC eval boards have dozens of high-Q
ceramics and multiple tantalums. So do our aerospace
customers' designs, and they know some stuff about
capacitor reliability. 5mV noise P-P, you're not going to
get with just one electrolytic.

Look at the noise as the "victim" sees it - where will you
attach the supplied circuit? There will be many different
results from probing between points, but only one pair
really matters. At least until you get to the case where
the input quantity of interest, is sourced from yet another
electrically distinct "ground".

 

[leo_o2]

Agree with dick_freebird, paralleled output capacitor will reduce ESR and DCDC output voltage ripple.
second，the ripple can be measured between the capacitor + and the -. It will demonstrate more ideal behavior. And EMI and noise coupling will lead to big spiking noise. It should be careafully optimized with PCB design.

 

[alimjoco]

Thanks guys. I checked on my lab and I probe it on the caps(+ and -) near the load end. In addition In dont use a passive prbe (although passive can be used just only remove the ground leads since it couples additional radiated noise). I used a BNC cable(50 ohm) terminated with 50 ohm input Oscilloscope..That is AC coupled. To be sure I used additional DC blocker between the DUT and scope. Is that a valid set-up???

 

[leo_o2]

DC block is not necessary if AC coupling is used for scope.
Bandwidth limiter can be turned on to reduce high frequency coupling noise.

 

[FvM]

In addition, paralleling output capacitors is the only way to achieve a suitable capacitance, ESR and current ripple capability. You may want to take a look at the CPU voltage regulators of any recent PC motherboard and reconsider about "bad practice". Paralleling capacitors of different value is somewhat unusual, and unreasonable from a lean BOM perspective, but not particular damnable.

Regarding the basic probing question. You are right about the problem with probe ground leads. Connecting a cable directly isn't a bad idea, but the 50 ohm load will attenuate high frequent "noise" to some extent. I also fear, that you get slightly different interference levels for each probing point. So it's a bit arbitrary to select one.

In my opinion, an appropriate probing location depends on the application and can't be determined generally.

 

[alimjoco]

I guess you are right, FvM. just a question though, I used a BNC in order to eliminate external/set-up noise outside the switcher itself. Don't you think it's more appropriate to use a well teminated connection such as 50 ohm cable with 50 ohm input AC coupled terminated scope rather than a probe with high input impedance Scope? My goal is i need also to check the high freq content of the switcher and isolate all necessary set-up generated noise.In that way i used a 50 ohm cable and 50 ohm termination in such a way there will be no reflections or standing waves seen in the length of the cable(i expect only the AC ripple and its noise coming from the switching transition). I also did check on my spectrum analyzer, it only consist of a fundamental freq(which is the ripple or switching freq) and the high orders of harmonics.Above 30Mhz, I dont see anymore high spectral freq content until 1 Ghz. Please advise.....Thanks ; By the way my switching freq is 600khz

 

[FvM]

Above 30Mhz, I dont see anymore high spectral freq content until 1 Ghz.

That sounds plausible. You will possibly see 50 to 100 MHz with fast switching devices. Fast passive probes can reproduce 300 or 500 MHz signal, and they don't show considerable reflections, because they use a resistive cable to supress them. But the probe impedance at high frequencies will be rather low.

For optimal signal reproduction without loading the source too much, a high speed resistive probe (50 ohm cable with 450 ohm to 5k series resistance) or an active probe would be preferred.

 

[alimjoco]

I did used active probes but comparing with a normal noise floor(without input), it has a quite a diffrence. Noise floor of FET probe in AC coupled is around 11mV pk to pk while BNC is around 3mv pk to pk. I did still see high freq content when I used the full BW of scope at switching nodes. But it was minimized. My only refernce on my ripple is my ripple formula and my plots on my spectrum analyzer. I guess spectrum analyzer is more an accurate approach because all freq bin is divided, and you can accurately see the freq content of each bin(peak detect mode). In time domain, its kinda confusing because you dont know if the noise riding the AC ripple is produced by the switcher itself or the externel set-up generated random noise(unless you are properly terminated)