DC Coupling of CML output

[mycw]

Hello everyone,

I was looking on a product datasheet and found something confusing me: on CML output, with 50-ohm pull-up resistors, "the input impedance of the following stage should be high", but why?

In my understanding, when we are simply considering RF signals, the equivalent input impedance seen by the transmission line will be a 50-ohm pull-up resistor in parallel with this high impedance next stage, which will be approximately 50-ohm again, but is it correct? Because apparently the results from ADS contradicts this hypothesis or maybe something is wrong configured in ADS? I used one 50-ohm terminal on the input side, and a large impedance terminal with 50-ohm pull-up resistor on the output side.

I really appreciate any comments. Thank you!


Mario Young

 

[biff44]

If you have a long run, you want to put those pull up resistors close to the loading gate. That way they act as individual 50 ohm termninations to the 50 ohm line, thereby reducing ringing on the line.

If your load was a low impedance, then the total load on any one line would be 50 ohms in parallel with some other impedance, so the total impedance would be less than 50 ohms. In this case, you would then have a mismatch, and you would get ringing from triple travel pulses.

 

[mycw]

It sounds to me the previous assumption that I made wasn't too far from the right path, but how can we probe it in simulation? Because I ran in ADS with a high-resistance output terminal (50K-Ohm), and its result is worse than 50-Ohm output terminal which is confusing me.

I have attached the schematic just in case there is something wrong that I didn't notice.

Thanks again!
Mario Young

 

[mycw]

Maybe I should add one more comment. Instead of having high load impedance, I noticed the performance is better by raising the impedance of pull-up resistor in my previous schematic (terminal 2 is kept to 50-ohm), and apparently it is contrary to the original explanation.