DC Contraints Query - how to constrain inputs and outputs

[vlsi_freak]

DC Contraints Query

Hi All,

I have a design which is purely combo.
The logic is given below,

first_out <= fixed and inputA;
sec_out <= fixed and inputB;
third_out <= fixed and inputC;

temp_output <= inputA and ext_input;

Here inputA, inputB, inputC are module inputs where inputA is asynch input and other two are synch inputs. The input fixed is coiming in synch from an external module.

The three outputs first_out , sec_out and third_out are outputs going from my module to different IP. Similarly temp_output is also an output from my module.

Here, how we constrain this inputs and outputs. Do we need to specify input and output delay here since, there is no sequential logic in my module using these input signals.

Please share ur ideas.

Best Regards.
freak

 

[shelby]

DC Contraints Query

If this block is synthesized and placed separately, then yes, you should specify input/output constraints. Otherwise the tools may just use the smallest cells driving large cap, and you will see bad timing results when you plug this module in at the top level.