1) You need max_fanout and max_capacitance to constrain the design , so that each cell can drive only a particular number of gates. Pleas look at the example below,
ex:-
If one of your AND gates is trying to drive 100 other gates, it might work for simulation but it will fail after fabrication. Because, every gate can drive only 10 - 20 other gates(assumption) based on their strength. So when you constrain
max_fanout and max capacitance in DC, it partitions the entire design to make sure every gate drives only 10 other gates. Hence to drive 100 gates, DC will replace the 1 AND gate with 10 AND gates.
I am not sure about 2 and 3. Hope that was helpful