[SOLVED] data type supports in SystemVerilog INTERFACE

[imbichie]

Hi All,

Can anyone tell which are the Data Types supported by the SystemVerilog INTERFACE.

For example can i use the Real, integer data types inside the INTERFACE or as an I/O ports in INTERFACE.

I wants to bring the UVM concepts in AMS Verification platform, for that i need to deal with the real, integer and electrical ports in the Verilog AMS and VHDL AMS.

 

[FvM]

The question suggests that you are asking about SV for simulation rather than synthesized logic. You can use all basic data types as well as structured types for interfaces.

 

[dave_59]

You will need to check with your simulation vendor about restrictions with data types on cross-language boundaries. Verilog-AMS although highly related to Verilog, is a different language.

 

[imbichie]

You can use all basic data types as well as structured types for interfaces.

Thank You FvM,
Let me know one thing, so whether it supports the Analog data types like wreal, electrical, voltage, etc,. ?

Also i need to know, whether the VHDL or Verilog (not SystemVerilog) can make use the UVM class concepts for verification ?

 

[dave_59]

UVM is library defined using SystemVerilog classes. Although your design under test may be Verilog, VHDL, SystemC, or anything else that can be instantiated like a Verilog module. The testbench however, must be written in SystemVerilog.

A SystemVerilog interface only supports those data types defined by the SystemVerilog language. It cannot have type like wreal, electrical, or voltage that only exist in Verilog-AMS.

You need to read your simulation vendors user manual to know how to connect models from two different languages together.

 

[imbichie]

Thank You Dave Rich