dick_freebird
Advanced Member level 7
I have been working on direct digital modulators and have
had a lot of trouble with getting a wide, high bandwidth,
source-synchronous data stream for test and characterization.
The last time, I ended up hand-wiring my own out of SSI
5V CMOS (because I could only find 5V EPROMS in the
speed grade I needed). A 10MHz reference clock is the
only RF-locked timing resource handy, anything else adds
jitter and/or spurs. We tried to use a fancy Agilent ESG
and found its interface (up to the PC and down to the eval
board) unworkable after weeks of trying with their apps
folks. We need something like an arbitrary waveform
generator, but the DAC is inside our part. Logic analyzers
we looked at, are too slow or narrow and can't be slaved
to the RF master tone.
If I could step up to 13MHz or 26MHz, so much the better
(would push that back into the spec an as an external
reference). Not an option with 70nS EPROMs, but ???
Basically it's EPROM holding digital amplitude words, and a
rolling programmable up-counter (w/ DIP switches for the
record length) which produces (say) sine and cosine waves
(for spurs testing) or I/Q modulation vectors for producing
standard modulation test patterns (for mask compliance
and such). I have not progressed to actually throwing real
time, modulated data through it.
I've considered (briefly) an FPGA approach, but know nothing
about FPGA tools and needed to get it done in weeks. This time
I have more slack. But a low-external-resources bench is nice,
and the EPROMs are that - power up, here's your GMSK mod
vectors a-rolling. If I had to go to a PC interface, I'd be out of
my depth again (but perhaps could use SRAM and get a better
word rate, using lower voltage logic and memory).
The last time was 8 bits wide, 64K deep. This time I will go to
16 wide (times 2 channels, I & Q) and same depth. I would not
handwire again, but get a PCB laid out (if not use an FPGA dev
kit, presuming it had the ~8MB RAM and 34 I/Os and a zero-
contributed-jitter clock that could lock to an RF source, etc.).
What I'm looking for is neat ideas, or even "done that", that
could be useful at bench test and maybe even integrate to
our PXI test racks (protocol and such, to be an exercise for
later, just a standard port at my end). It could be rented
test eqpt of a kind or grade we haven't seen, could be a
SSI lashup as before, could be an FPGA (rent some help) or
whatever.
had a lot of trouble with getting a wide, high bandwidth,
source-synchronous data stream for test and characterization.
The last time, I ended up hand-wiring my own out of SSI
5V CMOS (because I could only find 5V EPROMS in the
speed grade I needed). A 10MHz reference clock is the
only RF-locked timing resource handy, anything else adds
jitter and/or spurs. We tried to use a fancy Agilent ESG
and found its interface (up to the PC and down to the eval
board) unworkable after weeks of trying with their apps
folks. We need something like an arbitrary waveform
generator, but the DAC is inside our part. Logic analyzers
we looked at, are too slow or narrow and can't be slaved
to the RF master tone.
If I could step up to 13MHz or 26MHz, so much the better
(would push that back into the spec an as an external
reference). Not an option with 70nS EPROMs, but ???
Basically it's EPROM holding digital amplitude words, and a
rolling programmable up-counter (w/ DIP switches for the
record length) which produces (say) sine and cosine waves
(for spurs testing) or I/Q modulation vectors for producing
standard modulation test patterns (for mask compliance
and such). I have not progressed to actually throwing real
time, modulated data through it.
I've considered (briefly) an FPGA approach, but know nothing
about FPGA tools and needed to get it done in weeks. This time
I have more slack. But a low-external-resources bench is nice,
and the EPROMs are that - power up, here's your GMSK mod
vectors a-rolling. If I had to go to a PC interface, I'd be out of
my depth again (but perhaps could use SRAM and get a better
word rate, using lower voltage logic and memory).
The last time was 8 bits wide, 64K deep. This time I will go to
16 wide (times 2 channels, I & Q) and same depth. I would not
handwire again, but get a PCB laid out (if not use an FPGA dev
kit, presuming it had the ~8MB RAM and 34 I/Os and a zero-
contributed-jitter clock that could lock to an RF source, etc.).
What I'm looking for is neat ideas, or even "done that", that
could be useful at bench test and maybe even integrate to
our PXI test racks (protocol and such, to be an exercise for
later, just a standard port at my end). It could be rented
test eqpt of a kind or grade we haven't seen, could be a
SSI lashup as before, could be an FPGA (rent some help) or
whatever.
