data read write to DDR2 SDRAM memory between microblaze and custom IP using PLB Bus

[Makni]

Hi everyBody,

I implement an xps system by using the Bus PLB. My IP core is added to the system using Create or Import Peripheral...
I want to know how can Microblaze write several data to DDR2 SDRAM and how the IP core read all the data from this memory, modify it and write it back to DDR2 SDRAM via the PLB Bus interface.

Therefore, I would like to write the image data directly to DDR SDRAM from my custom IP core. However, I am not sure how I can get my custom core to write to the DDR using the PLB bus.
If anyone could point me in the right direction, I would really appreciate it. I know that I will need to make my custom core a "Master" on the PLB bus but I can't find a good example on how to read/write to memory.

Thanks in advance.

 

[shahulakthar]

In Xilinx Platform Studio, MPMC ip core is avaiable to access ddr memory. It implement Microblaze interfacing with MPMC core through PLB. When you point your linker script to DDR2 memory.

You can store image as array and do image processing algorithm.

 

[Makni]

In Xilinx Platform Studio, MPMC ip core is avaiable to access ddr memory. It implement Microblaze interfacing with MPMC core through PLB. When you point your linker script to DDR2 memory.

You can store image as array and do image processing algorithm.

Thanks for your reply. I have already write a data image to DDR2 SDRAM extern memory,

// get the base address of SDRAM memory extern to FPGA
int baseaddress = XPAR_DDR2_SDRAM_MPMC_BASEADDR;

 //declare a pointer to int (add4 to baseadress)
volatile int *txframe = (volatile int *)baseaddress;
*(txframe) = 56; 
*(txframe+1) = 41; 
*(txframe+2) = 56; 
*(txframe+3) = 41;
*(txframe+4) = 56; 
*(txframe+5) = 41;
*(txframe+6) = 56; 
*(txframe+7) = 41;

now, I want to implement a hardware accelerator using the VHDL code. This IP will access to this memory and get the values of data and do a traitement on this data..

Can you help me please.
Thanks in advance.