data from SDR design to DDR design

[sun_ray]

There is a design named SDR_module which can send data at 100 MHz and receive data at 100 MHz. This SDR_module only works at positive edge of clock. This design wants to send data and also get data from a design named DDR_module which operates both positive edge and negative edge and the operating frequency of DDR_module is 500 MHz.

Please provide some solutions.

 

[layowblue]

basic idea is to define/identify some hand-shaking signals if possible, like valid/ready. But since it's hand-shaking, the "slow" side will pull down the fast side in term of efficiency.
Also, you can try async-fifo as a buffer between the two clock domains.

 

[sun_ray]

basic idea is to define/identify some hand-shaking signals if possible, like valid/ready. But since it's hand-shaking, the "slow" side will pull down the fast side in term of efficiency.
Also, you can try async-fifo as a buffer between the two clock domains.

It is a transfer from a slow domain to faster domain. So what will be the depth of async FIFO?

Regards

 

[layowblue]

This question you should ask yourself, based on your targeting design feature.
Proper async-fifo controlling can pass data from fast-domain to slow-domain and vice versa.
But this is only a technical "tool" for you to choose if necessary. Your design goal, namely your feature/spec is the first and foremost item you should make crystal clear.
I'm feeling that you focus too much on details. Have a piece of paper and list out the features, then you'll be able to figure out whether you need async-fifo or if needed, how deep it should be.

It is a transfer from a slow domain to faster domain. So what will be the depth of async FIFO?

Regards