[SOLVED] DAC setup and hold time

[ilovephysics]

I am looking at the timing parameters for a DAC, AD9755.

https://www.analog.com/static/imported-files/data_sheets/AD9755.pdf

It has the following specifications:


input setup time: -1 ns (Min) -1.5 ns (Typ)

input hold time: 2.5 ns (Min) 1.7 ns (Typ)

First of all, since the setup time is negative, does that mean if I satisfy the hold time, I automatically satisfy the setup time in this case?

Secondly, why does it give me a typical value of 1.7 ns for hold time when the minimum value has to be 2.5 ns?

Thanks for your help!

 

[permute]

The issue of negative setup, large positive hold is confusing to most people the first time they see it. Basically, the clock and data will be delayed by different amounts. The end result is that, if the data is changed 0 to 1ns after the clock AT THE PACKAGE PINS, the setup time of the internal registers will still be satisfied.

Because the internal register do have a setup/hold window, this ends up with a very large hold time requirement.

The end result is this:
the data must be stable from 1ns AFTER the clock edge to 2.5ns AFTER the clock edge. this is a 1.5ns window that the data must remain valid. for some high speeds dacs, the hold time might actually be higher than the clock period -- this is fine as long as the data window is still less than the clock period.

 

[ilovephysics]

The issue of negative setup, large positive hold is confusing to most people the first time they see it. Basically, the clock and data will be delayed by different amounts. The end result is that, if the data is changed 0 to 1ns after the clock AT THE PACKAGE PINS, the setup time of the internal registers will still be satisfied.

Because the internal register do have a setup/hold window, this ends up with a very large hold time requirement.

The end result is this:
the data must be stable from 1ns AFTER the clock edge to 2.5ns AFTER the clock edge. this is a 1.5ns window that the data must remain valid. for some high speeds dacs, the hold time might actually be higher than the clock period -- this is fine as long as the data window is still less than the clock period.

Thanks! It helped!