DAC Jitter Modeling for CTSD Modulator

RamyRady_RF · Apr 20, 2019

Hello,

I was implementing a 5 bit DAC to be used in a CT sigma delta modulator. I would like to model the error due to clk Jitter at the output of the DAC in VerilogA. Any Ideas?

pancho_hideboo · Apr 20, 2019

Use ideal DAC and clock with jitter.

RamyRady_RF · Apr 20, 2019

pancho_hideboo said:
Use ideal DAC and clock with jitter.

Since, I am new to verilogA, could you tell me How to model Clock with jitter?

pancho_hideboo · Apr 21, 2019

See https://designers-guide.org/verilog-ams/functional-blocks/osc/osc.va

RamyRady_RF · Apr 22, 2019

Hi,

Do you know How to add mismatch to the DAC Model that calculates the value each clock?

Thanks

pancho_hideboo · Apr 22, 2019

RamyRady_RF said:
Do you know How to add mismatch to the DAC Model that calculates the value each clock?

Generate random number.

DAC Jitter Modeling for CTSD Modulator

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DAC Jitter Modeling for CTSD Modulator

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