Hi,
In my eyes: If you want to design a DAC, you should get/have/decide the specification first.
It needs to tell you about
* the interface (signal levels, timing, serial, parallel, differential...)
* the DAC type (R2R, Delta Sigma, resolution,....)
* and the electrical specifications of the analog signal (voltage, current, levels, noise, timing, accuracy, INL, DNL ...)
If you have this specification, all the questions above should be answered.
To the questions in detail:
1) The usual signal to a DAC is a binary signal with logic levels. Your question whether A or B more sounds if the bits come as serial datastream or parallel. Both is usual. Serial may be: I2C, SPI, I2S, LVDS ....They may come in single ended as well as differential.
2) Now think about it as serial...one bit after the other. If now comes the first bit of a dataword...what do you think should happen to this bit at the R2R dac ... and what shoukd happen to all the other bits of the R2R DAC (should they keevp previous state or start with a preset value? And now think how the analog output will look like (in time, bit after bit) when this happens.
(As so often I recommend to use a sheet of paper and a pencil or any software (even Excel will do) to "simulate" your idea.
No need for exact timing or exact voltage levels ... )
I assume (independent of the scenario you think about) this will not give satisfying analog output.
Thus I see only two meaningful solutions:
* update all digital inputs to a R2R ladder at the same time (preferred. Simple shift register)
* or use an analog "hold" circuit at the analog output
Klaus