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D5 violation (DFT) MENTOR GRAPHICS

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dft_guy

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Simply - make sure your whole circuit is scanned - a D5 means you have non-scan flops. If DC has turned out a circuit that has non-scanned flops, then it means it either could not control all the clocks and resets to the flops, or somebody put a 'dont_touch' on part of the circuit.
 

gold_2007

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dft_guy said:
Simply - make sure your whole circuit is scanned - a D5 means you have non-scan flops. If DC has turned out a circuit that has non-scanned flops, then it means it either could not control all the clocks and resets to the flops, or somebody put a 'dont_touch' on part of the circuit.

How can i make nonscan flop scannable
 

dft_guy

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Well, I don't know what part of the flow you have access to, but in my environment, I send it back to the designer, and work with him/her to resolve the reasons for the non-scan circuitry. Like I said, the main reasons for the synthesis tool not including certain flops in the scan implementation are:

1) The clocks/resets to those flops are not controlled. The control circuitry needs to be changed to fix it.

2) For some reason, the flops were 'dont_touched' during scan insertion. Sometimes this is intentional in order to achieve timing closure, or to save area/power.

First find the reason, then figure out how to resolve it, if it is resolvable.

John
DFT Digest
 
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