D latch using wait statement

Hi,

I am newbie to Verilog.
How do I write a code for a D latch using wait statement? (latch that takes clock and d
as inputs and q as output. q = d whenever clock = 1.)

I tried the code below.

//design
module DFFlevel(clk, D, q);

input clk,D;
output q;

reg q;

always
begin
wait(clk) q <= D;
end

endmodule
//end of design

//testbench

module test;

reg clk,D;
wire q;

DFFlevel DFF(clk, D, q);

initial
begin
$monitor($time," %b, %b, %b\n",clk,D,q);
end

initial
begin
clk = 1'b0;
D = 1'b0;
end


always #2 clk = ~clk;

always #5 D = ~D;

initial
begin
#30 $finish;
end

endmodule
// end of testbench

But when I execute the code, the time is not advancing beyond 2ns.

Now, if I modify the wait statement by adding a delay,
"wait(clk) #1 q <= D;"
the outputs are coming fine.

I do not understand the significance of delay here.
Can anyone help?

I am using iverilog for coding.


Thanks in advance.

hi...,
wait statement is not synthesizable even if you can stimulate it in software point of view u can not infer wait statement to any of the latch or flip-flop so i think using wait is not advisable or else you might face problem while synthesizing it

this is the best way to write a verilog code for D-latch(as per my knowledge)

module d_latck(clk,d,q);
input wire clk,d;
output reg q;

always @ (clk)
begin
if(clk)
q=d;
else
d=d;
end
endmodule




i hope u migt have understood something what i was trying to tell you

use always @ (posedge clk ) in the above program it is not always @(clk)....................... i hope this may work