D Flip-Flop with Negative-Edge Clock or Positive-Edge Clock

[voho]

Hi all,

i use ise foundation i want to use D Flip-Flop where you can chose with Negative-Edge Clock or Positive-Edge Clock.

i found FDC_1

Thank's in advance

 

[masai_mara]

Re: D Flip-Flop with Negative-Edge Clock or Positive-Edge Cl

Xilinx fpgas dont have different edge triggered FFs. If you say neg edge then it just adds an inverter before the pos edge FF.

 

[bibo1978]

Re: D Flip-Flop with Negative-Edge Clock or Positive-Edge Cl

I want to demonstrate that the inverter is not added externally, it is added internall, i.e. through a programmable mux with in the CLB, check out Xilinx FPGA for more details, the main issue here is that the LUT output will suffer very large skew and will affect your design badly.

 

[Big Boy]

Re: D Flip-Flop with Negative-Edge Clock or Positive-Edge Cl

The clock input of a flip-flop can be inverted or not, without passing via a LUT. For example, in Spartan-III device, at the input of a slice, the clock pass through a programable mux, which select between clk and ~clk (this isn't visible much within the datasheet, but if you look with FPGA editor, it is obvious). However, wether inverted or not, that clock then go to both flip-flop of that slice. So, both FF either use clk or ~clk. The map tool will take cere of this.

 

[Prasanna Kumar]

Re: D Flip-Flop with Negative-Edge Clock or Positive-Edge Cl

The Clcok is one, when u say -ve edge u have already done it in the code, specifying a negative edge triggering by keeping an inverter to the incoming clock.

 

[Kulprashant]

hi,
according to coding style it will give you the flipflop type.
for example:
clk'event and clk='1'
=>pos edge ff
clk'event and clk='0'
=>neg edge ff

with regards,
kul