D flip-flop simulation problem

[yann_sun]

Hi,

I run some simulations on a D flip-flop.
If input signal D changes at the active edge of CLK of the DFF, it's obvious that output will delay a cycle.
But when D and CLK separately connects to a IO pad whose delay is 1ns, I get a different result that output Q follows input D without any delay.
Could you please explain why it happens and what I should do if I want the one-cycle-delay output? Many thanks.

 

[YuLongHuang]

I'm not sure if this called ""race condition".
The simulator doesn't know which one should be execute first since they are at the same time stick.

Back to your question, since the D and CLK are pass through IO pad and there are delay for both signals.
Which one is arrived first ? D or CLK ?

If the D is arrived first, the CLK will sample this D and output the signals as the same as input.
However, if the CLK is arrived first, the CLK will sample the previous D and output the signals which is the old D.

Basically, this type of modeling will cause such problem since in real case this is called setup time violation.
This also means that your original modeling is improper so it's better to change it as my thought.

 

[fouwad]

which simulation tool r u using? u must use a real time simulator for eg the post route simulation mode in xilinx to observe delays in ur simulations