rudyb
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Hi,
I am working on a ZedBoard, which essentially has a Zynq FPGA, with two 16-bit DDR3 SRAMs, which are configured in parallel to form a 32-bit 'virtual device' with common address and control connections.
As I just mentioned, unfortunately, the two DDR dies are not separately addressed.
I would like to know whether it is possible to treat these two as seperate DDR components?
In other words, I would prefer to control the data that is written into RAMS. For example, I would like to target only one of the DDR dies, and I would like to leave the other one untouched.
Is this doable, knowing that the board is configured as parallel combined address line? How can this be done?
Thanks,
--Rudy
I am working on a ZedBoard, which essentially has a Zynq FPGA, with two 16-bit DDR3 SRAMs, which are configured in parallel to form a 32-bit 'virtual device' with common address and control connections.
As I just mentioned, unfortunately, the two DDR dies are not separately addressed.
I would like to know whether it is possible to treat these two as seperate DDR components?
In other words, I would prefer to control the data that is written into RAMS. For example, I would like to target only one of the DDR dies, and I would like to leave the other one untouched.
Is this doable, knowing that the board is configured as parallel combined address line? How can this be done?
Thanks,
--Rudy