current starved inverter vco

[scooby-doo]

Hey all,

I want do design a current starved inverter based vco.
to achieve a linear voltage-to-frequency transfer characteristic i built already a linear voltage to current converter which supplies the input current for the vco.
this current is mirrored by simple current mirrors into the vco.

i designed the pmos transisotrs to be 10/1 and the nmos transisors to be 5/1.
(1 is the shortest lenght in process)
this allows me equal delays for rising and falling edges and an equal current in the sourcing/sinking device during transition.

as far as i know the frequency is determinded by fosc=I/(N*C*Vswing)
where I= current through inverter
N=number of stages
C=parasitic capacitance of inverter
Vsing=Voltage swing of inverter.

therefor I assumed a linear relation between my input current and the oscillation frequency.
but if I look at my transfercaracteristic I see a perfect quadratic behaviour between current and frequency. it´s looking close to linear but there is still a visible arc within my transfer characteristic.

does anyone know where that could come from and what i could do to make in more linear?

 

[BradtheRad]

I'm not familiar with the topology you are using, although I too had a problem getting linear performance from a V to F oscillator I was making for a meter.

I needed a straight V-F graph over a 1:100 range or better. Up to 9 V input. It was a challenge.

I tried some vco circuits I found in books. Didn't suit. Either the V vs. F graph always had a curve to it, or the circuit didn't operate down to zero V input.

I managed to design my own. Charging a capacitor til it reaches .09V, then discharging quickly to zero. But now it had a threshold of .09 V input. Below that my meter did not read.

I found that the larger capacitor I use, the more it needs ample charging current. Especially at faster frequencies. This was not something I would know to predict from the simple RC time constant formula.

This means series resistance can become more of a problem the greater you try to extend the range of the oscillator. Unexpected resistance from somewhere.

Transistors may approach saturation. Diodes and other components have a minimum 'ON' resistance. Etc.

Capacitors can develop internal series resistance. Or internal parallel resistance. Etc.

A similar problem applies to coils. A small coil needs more current to yield the same time constant as a large coil using less current.

Just my thoughts. I don't know if this is affecting your linearity.

 

[dgnani]

Hey all,

I want do design a current starved inverter based vco.
to achieve a linear voltage-to-frequency transfer characteristic i built already a linear voltage to current converter which supplies the input current for the vco.
this current is mirrored by simple current mirrors into the vco.

i designed the pmos transisotrs to be 10/1 and the nmos transisors to be 5/1.
(1 is the shortest lenght in process)
this allows me equal delays for rising and falling edges and an equal current in the sourcing/sinking device during transition.

as far as i know the frequency is determinded by fosc=I/(N*C*Vswing)
where I= current through inverter
N=number of stages
C=parasitic capacitance of inverter
Vsing=Voltage swing of inverter.

therefor I assumed a linear relation between my input current and the oscillation frequency.
but if I look at my transfercaracteristic I see a perfect quadratic behaviour between current and frequency. it´s looking close to linear but there is still a visible arc within my transfer characteristic.

does anyone know where that could come from and what i could do to make in more linear?

Assuming you have thoroughly checked the linearity of the V-I converter, I see two options:
- the current mirrors of the starved inverter are inaccurate during part of the transition e.g. the current is too large for the on resistance of one of the switches so it pushes the current mirror out of saturation OR the Early effect is too large
- the gate capacitance is too non-linear in the range you are using it, check the dynamic capacitance of the input of your starved inverter

Let us know