current source for the layout design

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preethi19

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Hi i am just starting to learn about layout design. I am trying to do the layout for a circuit. In the schematic i have run the simulation using a current source. The current source positive is given to the gate of a nmos and the -ve terminal of the current source is connected to vdd or can be grounded. So when it comes to layout how am i supposed to do this. Should i just leave the gate of the transistor as an input pin? so wer the current source can be connected to that pin separately. And for the negative terminal which i can connect to vdd or gnd should i leave any space for that. I'm doing my layout using cadence. Thank you!!!
 

You can not lay out any ideal sources right!!. Ideal source is ideal, not practical. Layout will have only what can be fabricated. During back annotation(post layout) sims, the block is usually considered as a black box. You will not have access to the internal nodes of the circuit, unlike in the case of schematic simulations. So, keep port pins on the nodes you want to have external excess to. You can continue using the ideal source in your test bench.
 

You can try replacing the current source by a resistor and then can mirror the current using mirror topology.
Calculate the resistor value as per the required current.
 

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