Current Mode designs are extremely becoming popular now. I invite a general comparison of it with voltage mode designs.Any highlights on the advantage & disadvantage of both methods would be beneficial.
the main advantage of current mode design is that signal is unattenuated while being transmitted through a resistance which is the most significant factor of most components... whereas voltage when transmitted gets attenuated due to resistance which cannot be avoided...
what are you meaning by conductive loss... because whether it is a capacitor or inductor or resistor that is modeled in the transmission line it is gonna be in parallel and hence the current is not going to be reduced...
Thanks for the discussion.
Plz enlighten me comparing the followings in voltage with current mode.
1.voltage swing/current swing
2.input range
3.impedance
4.slew rate
5.linearity
You can also give me related lectures/tutorials in pdf/link.
Thanks again
hi all
i think the posts above misunderstand what the first author want to discuss.
some people talked about the conceptions of voltage mode and current mode, these i think used mostly in power electronic ic domain.
but i think the first post want to know is, in general analog ic part, what is the difference between voltage and current mode.
Thanx to all those who have participated in the discussion & shared their resources here.
Jfyan is also right that I m seriously interested in Analog IC part mainly.But every contribution has enlightened me in their own way.
Thanx again