Current mirrors in sub-threshold region

[diarmuid]

Hello All,

Is there any reason why one would not want to operate FETs of a current mirror in sub-threshold region?

It seems attractive for the following reasons:

- High output impedance
- Low gm so lower noise

Doesnt seem to be too common so Im just wondering why.

Thanks,

Diarmuid

 

[erikl]

I often used sub-threshold mirrors. The only refutation is silicon area consumption, IMHO.

 

[dick_freebird]

If you don't need the last bit of headroom then subthreshold
wastes area. One other issue is, how low can you go before
leakage currents become too variable (process, temp) to keep
mirror fidelity. The higher your upper temperature limit, the
less deep into subthreshold you can reliably go while keeping
matching or even gross setpoint. Wider = leakier.

What do you know about current match across Vgs? Often
we only get VT-match information which is fine at / about VT
but not necessarily useful when you get decades away from
where the data is.

I have encountered more than once, technologies with a "gate
kink" in the subthreshold region. Often this is due to bird's beak
or STI edge issues. If there's anything like this, you can expect
it to vary unpredictably and you may step right into it, with a
pretty bad matching impact. You have to stay well above the
kink for any consistency in production, and you may not know
the range without a lot of (unpleasant) history.

Lastly if the drains of that mirror rack are "busy", a very low
pilot current means a pretty high gate-node impedance and
the mirror rack may be harder pressed to stay on point against
dynamic perturbations - made worse because the ratio of
Cds to operating current is higher.

 

[diarmuid]

Excellent feedback. You seem to have had a lot of experience operating FETs
in subthreshold. Just some questions to clarify:

I have encountered more than once, technologies with a "gate
kink" in the subthreshold region. Often this is due to bird's beak
or STI edge issues.

If I increase my LOD (as I would be for a mirror) wont this reduce
such edge effects as this kink?

Lastly if the drains of that mirror rack are "busy", a very low
pilot current means a pretty high gate-node impedance and
the mirror rack may be harder pressed to stay on point against
dynamic perturbations - made worse because the ratio of
Cds to operating current is higher.

Im afraid I dont quite understand what you mean here. What do you
mean by "busy" and what is a "pilot current".

Thanks a million,

Diarmuid

 

[dick_freebird]

Increasing L may mitigate the edge related kink or move it
up and down, left and right. But you always have that sliver
of lousy oxide at the edge (unless you go to edgeless or
channel-stop designs) conducting at a different Vgs and
with a different subthreshold slope and surface-state floor
for leakage. Only by making the edge a much higher VT
or much lower surface state density can you bury its
effect.

By "busy" I mean, not slow continuous-time analog but
seeing switching / high dV/dt activity. This can pump
the mirror-rack gate node and only the pilot current (the
bias current sourced into the rack, that you are mirroring
to N locations), or the reference device's drain current
(which ought to roughly equal the pilot current) can pull
the rack back to setpoint. This can take a pretty long
time at very low power, and give you things like long
settling-time tails (bad for high bit count fast ADC/DAC)
or excess phase noise (PLL charge pumps where history
can alter the per-cycle charge delivered) or funky poles
you see in large signal but not small signal analysis.