current mirror size vs current value

[AMSA84]

Hi guys, I need to design a current mirror to mirror a current from a ptat + ctat current source.

The questionar is:

My current source has a current reference of 12uA. Aeound that and I want to mirror this current to a sawtooth generator in which is to work at 500MHz.

The problemas here is that this sawtooth generator requires a 1mA current to charge the capacitor (90fF). The comparator that I use in this uses a 300uA current and this current is to be obtained from T
The same current source.

So the big question is this:

There is any problem to get the 1000uA current from the 12uA current reference? It is a ratio of almost 1:90. There will be any problemas in layout or so? Maybe using this current source (right now I AM with an ideal one) with this size will be slow to deliver the 1000uA current because of the speed frequency?

Kimd regards.

Is there any problem having the same current source that will supply the current to he sawtooth generator to the other blocks?

 

[dick_freebird]

A very large current ratio will make the response slow,
because you have a huge Cgg and a small pilot current
to swing it. The output dV/dt will fight the gate voltage
through Cdg and while slewing you are unlikely to get
the desired out:in ratio of current.

A buffered current mirror could be "stiffer" and you may
be able to do some peaking, which is probably necessary
at the frequency you want.

I'd separate the comparator and the cap drive current
branches further back to avoid any switching related
"stuff" on the comparator bias. The cap charging mirror
might want its ~80:1 gain taken in multiple, lower ratio
steps.

I might recommend that you not try to switch that charging
current to zero, but instead a low "pilot light" level so that
you do not have to charge up to VT from nothing, before
you get current. Consider a switched shunt on the gate
line of the final, which toggles you between (say) 1X
and 16X gain; eat the 1X by making the discharge current
larger accordingly and constant-on.

 

[AMSA84]

Thanks for the reply.

What about then doing a separated current source to charge the capacitor, having a DC current reference around 100uA? This way would represent a 1:10 ratio. What you think about it? (I tried that , using simple idc source with 100uA and then mirrored).

By the way, I am facing another problem, that is:

I am using right now an analog lib capacitor in the sawtooth circuit. In the sawtooth generator, the circuit only works if I put a initial condition of zero.

Do you have any idea on how can I put the circuit working without the initial condition to zero? I ask that because I will be moving to a MOM or MIM cap and there I can't use an initial condition.

I don't have a clue on this.

Regards.

 

[dick_freebird]

In my book the proper way to force an initial condition
is explicitly, in the circuit design. Use a power-on-reset,
master reset or even your own poor-boy startup if these
are not available. Ought to cost you two transistors, if
you used a SRFF as the master then an additional input
on one of them that gets a reset initially, would do it.
A tighter design, maybe just a strategically placed shunt
FET.

Trust me, when things get real on the test floor you
will be happy that initial conditions are explicit rather
than imaginary.

There's probably some tradeoff between housekeeping
currents, capacitor size and sawtooth qualities but I do
not know what your values are, to judge.

 

[AMSA84]

Thank you so much for the reply freebird.

So in other words what you are suggesting is to implement a circuit, simple, with some digital logic that forces the capacitor initial condition to be zero?

Can you elaborate how to implement the power-on-reset, master reset?

I am not using anykind of FF in this circuit. Basically, the circuit is something like this:

**broken link removed**

 

[AMSA84]

By the way, what you mean by:

I might recommend that you not try to switch that charging
current to zero, but instead a low "pilot light" level so that
you do not have to charge up to VT from nothing, before
you get current.

?

Is having a current mirror that discharge the capacitor at a constant current?

 

[dick_freebird]

You can switch the charge and discharge. But you can
also switch only one, bilevel, against a fixed source /
sink and get the same result (aside from that, in one
phase, there will be some waste). Like, say, a 100uA
fixed source, and a bilevel 50/600uA sink would (net)
give you 50uA source, 500uA sink applied to the timing
node. The primary benefit to this application being, you
do not fully turn off the sink driver with its higher Cgg
and then have to snap it on speedily - it's always on
and only a hundred mV or so slew is required. Much
better than 500mV to reach setpoint, from zero (and
similarly, on the turnoff edge). Of course during the
sink phase you would be eating that other 50uA. But
when fast current value / direction switching is desired,
that may be a secondary concern.

Re the POR - you said this is going to be integrated,
whatever you are integrating with may already have
this resource. Ask your team-mates? If no, this function
can be easily designed (less easily, when you care a
lot about what happens between zero and some min
VDD - when nobody's got a VT to work with, funny
stuff happens and is prone to be process sensitive).
Still, if there's any significant logic, or even stuff like a
voltage reference onboard, there is probably opportunity
to steal a useful signal.

 

[AMSA84]

Okay then. I understood.

Right now I am successful to put my sawtooth generator working. You can see here:

**broken link removed**

The schematic that I used was the one that I have posted above. At same time I managed to put another circuit where I used a not gate (cmos) which the output not is connected to the capacitor. Here:

**broken link removed**

But I am facing some problems (that I think it is "easy" to solve) regading the voltage level (lower and upper) of the sawtooth. Since I got the "one switch" sawtooth circuit working, don't know if it worth waste some time on the sawtooth with that not (cmos) gate.

Forgive my insistence (but that's because I think it is an interesting idea):

"You can switch the charge and discharge. But you can also switch only one, bilevel, against a fixed source / sink and get the same result (aside from that, in one phase, there will be some waste). Like, say, a 100uA fixed source, and a bilevel 50/600uA sink would (net) give you 50uA source, 500uA sink applied to the timing node. The primary benefit to this application being, you do not fully turn off the sink driver with its higher Cgg and then have to snap it on speedily - it's always on and only a hundred mV or so slew is required"

Can you explain in other words? Maybe is my understanding that is uncapable of realize what you want to say.

To finish, the POR has anything to do with the softstart of the system?

I will be wating for your opinion on that sawtooth.

 

[AMSA84]

Hi guys.

I have improved my current reference and right now I have the following:

20uA reference. The transisor that mirrors the current that was previously summed from a PTAT and a CTAT source have a size 5/1.5um (NMOS transistors). After that I mirror again to transform this current source to a PMOS type reference. The PMOS have a size of 25/1.5um. This summed current referente has 20uA.

Now the question is: this current reference is to bias a OTA around 200uA. Here se have a ratio of 1:10. It will bias a comparator. He has a bias current of 170uA. So here the ratio is less thant 1:10. Those transistors have a a size around 30/1.5um.

Nos the question here is this: I need to supply a current around 600uA to a comparator. The transistor size is around 100/1.5um. The current ratio here is 20uA to 600uA that is 1:30.

IS THERE any problemas with this? I read that the ideal ratio should be around 1:10.