Current mirror in subthreshold

[deveshkm]

Hi,
I am designing a differential amplifier for Vdd=1.5 to 1.7 V
Input is PMOS
In order to meet the specifications over PVT and icmr
I biased diff pair in subthreshold. However, due to limited headroom I reduced VDSAT of tail MOS by biasing in subthreshold
I have obtained sufficient bias margin to keep every device in saturation, albeit subthreshold
What are the possible drawbacks of using subthreshold current mirror?

 

[dick_freebird]

One issue is the generally poor modeling of leakage floor and
subthreshold slope and the transition between these regimes.
Your mirror current has to "bury" any leakage current by some
decades, if you want ultimate fidelity, and you can't know this
from models (unless your foundry takes such things very
seriously, which a "digital" flow would probably not).

 

[frankrose]

For current mirrors better to keep transistors in saturation with lower gm values, it helps when mismatch comes into play.
If the Vdsat is higher the mirrored current will be more unsensitive to mismatch of threshold voltages between the diode and the mirroring device.