Current mirror design

[Yarrow]

current mirror

Hi all.

I was wondering if anyone knows what the best way of achieving low input impedance and high output impedance in a CMOS current mirror?

The input of the current mirror is connected to the output of a current steering DAC, and the output of the current mirror is connected to a comparator.

Please correct me if this does not make sense.

 

[dick_freebird]

mirror design

For low input impedance, make the input be the
source of a source-follower and the drain goes to the
current mirror pilot device (or stack). For high Zout,
use a cascoded mirror or source degeneration, try
them both to see which plays better with your desired
attributes (supply current, bandwidth, matching w/
foundry device tolerances etc.).

The IDAC probably wants a very constant input
voltage as well as impedance, so it may want a
layer of feedback control at the source follower
gate such that Vin remains at null across the code-range
and externalities (supply, temp, process).

 

[Yarrow]

mirror current

Sorry for the late reply. Tnx for the help. I did some work on the current mirror, and found a good fit, being a current mirror with active feedback. Although I got issues with noise in the DAC, but thats another story.

 

[eld03]

designing of a current mirror

Try regulated cascode topology.