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However, in this case it seems that you have a basic current mirror with mother transistor having
the W/L of M1 & M3. Same for the M2 and M4.
I have seen such schematics of two "series" transistors with the idea to have the effect of a single
transistor with twice the length.
It is a self-cascode CM but with a few conditions. If all mosfets has the same threshold voltage, or the same type and floats in the same well, this CM can be threated as simple CM with equivallent length equal to sum of each stacked transistor. If mosfets closer to rail (M2, M1 in this case) has higher threshold voltage and the differences in Vth is higher than Vdsat of M3, M4 than overall circuit is equivallent to cascode CM.
First time it was proposed in paper published in 1998 about Sigma-Delta Modulator in IEEE Journal - solid state or CAS but I don't remember exact title.
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