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[SOLVED] Current mirror circuit with Gates connected

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1mace1

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Hello,

attached you see a current mirror circuit.

I do not understand for what reason are the gates of the upper pmos devices (M3,M4) connected with the lower ones (M1,M2)?

Should the upper transistors work like a source-degeneration resistor?
 

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Hi,

this topology seems very familiar as with the cascoded current mirrors
https://www-soc.lip6.fr/~hassan/lec6_cur_mir.pdf (random link on the web)

However, in this case it seems that you have a basic current mirror with mother transistor having
the W/L of M1 & M3. Same for the M2 and M4.
I have seen such schematics of two "series" transistors with the idea to have the effect of a single
transistor with twice the length.
 

It is a self-cascode CM but with a few conditions. If all mosfets has the same threshold voltage, or the same type and floats in the same well, this CM can be threated as simple CM with equivallent length equal to sum of each stacked transistor. If mosfets closer to rail (M2, M1 in this case) has higher threshold voltage and the differences in Vth is higher than Vdsat of M3, M4 than overall circuit is equivallent to cascode CM.

First time it was proposed in paper published in 1998 about Sigma-Delta Modulator in IEEE Journal - solid state or CAS but I don't remember exact title.
 
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    1mace1

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anyone knows what the name of this paper? thanks.
 

I've seen something very similar (if not the same thing-I don't remember at the moment).

You could connect the gate of M3 to the drain, but in that case, your maximum output voltage will be limited to Vout=VDD-VT-Vov

Whereas in the case you have shown it will be limited to Vout=VDD-2Vov
 

Actually yes, a low threshold voltage (or depletion) transistor may do the cascoding job.
 

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