Schematic does not show the gate stimuli for the circuit.
Also your L2, L3 should be coupled inductors (xfmr) with
an output winding, bridge and inductor not shown. The
negative swing may have to do with the inductor not
being coupled to the opposite primary leg, its negative
clipping voltage may be the D-B diode of the FET
conducting (generally Not A Good Thing). The primary
should see swings between GND and V_DC*2 in a
voltage fed mode; what the L1 inductor does, I'm
unfamiliar with.
The near zero L1 current may be because there is no
energy taken off the system (secondary, load) so all
there is, is shuttling losses from switching the primary?
If everything is ideal-ish then a trivial input current
would be a normal outcome.
I think I'd start with the xfmr/bridge/load model and
the gate drive particulars. Make it as realistic and
application-appropriate as you can. Plot the two drain
voltages and the center tap point. Maybe that would
show some clues.