Current Drop in when LNA is saturated

[inass57]

Hi guys,

I'm using a commercially available amplifier with the recommended PCB layout, We have noticed that when we put an input power that would push it into the saturated region, the current drops out from 120mA to somthing between 30 and 60mA. Why do you this is the case?

Thanks in advance.

 

[FvM]

You can probably explain it in detail when looking at the schematic. I guess, the input signal is rectified by the input transistor and the bias point is shifted to lower quiescent current.

Quite generally, unless explicitly granted in the specification, LNA are not designed for saturated operation, recovery time may be long.

 

[inass57]

Can you please explain how the input signal can change the Bias point? do you have any documentation about this kind of phenomenon?

As i understand it an LNA is a class A amplifier, and its bias point should not be dependant on the input signal.

 

[FvM]

Saturation means leaving the class A range.

 

[vfone]

If the current drops from 120mA to 30mA means you have to avoid the saturation region of the amplifier, by using less input power (probably the gain of the amplifier drops many times in the current drop situation).
IF the amplifier supports higher current and you want to use high input power, you have to increase the quiescent current of the amplifier, and saturation will happen at higher input level. But have to check what is the current limit of the amplifier.
If is a multistage amplifier bias line impedance (filtering) may play an important role avoiding current drop vs input power.

 

[inass57]

If is a multistage amplifier bias line impedance (filtering) may play an important role avoiding current drop vs input power.

the thing i noticed is by changing the input impedance (i added a filter before the amplifier and compensated for the filter losses) the current drop is not the same, i have 20mA drop instead of the 60mA.
I also did combine a pulse that will saturate the amplifier with a CW that will keep the amplifier in the linear area. doing this i have a recovery time of almost 2ms, when i put the filter at the input this recovery time would disappear.

I find this very curious. and have a hard time undestanding how the input impedance have this much in pact on the recovery time and on the current.

 

[vfone]

This phenomenon is named "bias settling time" and happen when use dynamic bias.
Optimizing the bias level not only during power-up and power-down but also during regular operation can improve the performance of the RF amplifier.

 

[Hawaslsh]

Hello,
The more experienced folks can correct me if I am wrong. For me, a good way to visualize why over driving an amp would cause a reduction in Id can be seen in the IV curve and load line.

please excuse hand drawn IV curve. The red represents your load line under low drive. Since its Class A you're quiescent point is in the middle of the red line. When you read a current, its the time average of Id, and as you begin to drive it extra hard, there are times your current will drop or even go to zero.

Take that with a mountain of salt. I'm still learning myself.