CTM layer error in cadence layout

[preethi19]

Hi i did my layout and cleared all DRC, LVS very properly without any error. My final step was to add pads to the layout design. I have attached an image with two final designs. I was given an example which is on the left to get an idea of how to add pads. The design on the left was fabricated and tested and worked fine. So i just removed the design on the left and added my design as shown in the right. This was wat my colleague suggested. I am getting the errors i have attached in second image.


Could anyone kindly tell me
i) What is CTM layer and why do i need that. I searched online but not much info. Also when i remove this layer i am clearing this error. So in order to clear this error should i just remove all ctm layer. Why is this layer added???

ii) I dont have any pins on a same net with a different name. I checked many times and i also had my LVS passed. All i did now was to take that design and remove the design on the left and just add my design and connect it to the pads.

iii) substrate/well soft connected- I have given VDD, GND connection then still why this error. Pls help!!!

iv)Pad pitch- I am assuming this i just need to check with CMC and if they are fine with the pad pitch i can ignore this error.

Finally below whole blocks of metal3,4,5 and 6 layers on top of one another is used to fill the empty space below the design. Is this really important. And why only metal 3,4,5 and 6... Why not other metal layers like 1 and 2?

Can anyone plssss help!!!! Tried it many times not able to correct these errors. Thank you!!!

 

[erikl]

i) Layer names are process and foundry specific. Check your PDK docu for their meaning. CTM layer must have to do something with metal layers.

ii) & iii) May be subsequent errors.

iv) Normally not allowed (bonding!)

v) For sensitive metal layers 1 & 2 this is usually done during mask data preparation

 

[NiedeLu]

You are working on TSMC PDK I guess? Usually this Layer is used to form MIM Caps. It is a special layer that is used in process options that offer this kind of Caps.

 

[preethi19]

Thank you erikl for your reply!!!
I read many posts and searched online and have some idea of why CTM layer and about the rest of the errors. CTM is a layer used in MIM. (Metal-CTM-Metal). This MIM is a parasitic capacitor and from one post i found is used for the purpose of insulation. But in my layout example due you have any suggestion on why they have only used the CTM layer without any top and bottom metal. It seems like they just wanted the insulator (CTM) layer and didn't want to form any actual MIM capacitor. Seems more like for the purpose of insulation. But the error i attached showed ctm outside metal 5 which seems like an error that would occur if i used a bottom metal layer of say metal 6 since i found a document for tsmc the rule was that the bottom metal cant exceed 5. But i cant see any metal layer with the CTM layer.

Also I only couldnt get the explanation of using metal 3,4,5 and 6 to fill out the empty space and why not metal 1 and 2. I understood what Mask data preparation is but what has that got to do with metal 1 and 2?? Could you pls help in this part!!! Thank again!!

 

[NiedeLu]

You need this metal layer underneath your CTM (Capacitor Top Metal) because the thin isolator is build on top of the metal. Otherwise the layout can not be fabricated:

http://amarketplaceofideas.com/wp-content/uploads/2015/03/XH018-MIM-Capacitor-Cross-Section.png

I guess you have an 6 Metal process: Metal 5 -> Bottom plate and via Metal 6 you connect your Top plate. If there is no MIM cap needed for the design you also need no CTM layer.

BR
Lukas

 

[erikl]

I ... couldnt get the explanation of using metal 3,4,5 and 6 to fill out the empty space and why not metal 1 and 2. I understood what Mask data preparation is but what has that got to do with metal 1 and 2??

Metal (and other superimposed) layers' filling percentage usually is related to your full design (chip) area. Metals 1 & 2 , which are the main routing metal layers for intra- and inter-cell routing, may already have/had enough metal filling to meet the percentage demands for your chip, so aren't reminded for further filling.

Anyway, it makes good sense to fill out the empty space below the MIM cap: with parallel cap(s) of the same (MIM) area.