An AT-cut Xtal has many properties related to, initial tolerance, temperature and aging. These three numbers affect the pulling range and offset from ideal f. Vdd can also affect the ESD diode and gate capacitance slightly. As well, vibration and shock can greatly affect the motional capacitance in femtofarads and frequency much greater.
A wide range of load caps can span over 500 ppm total range, with a greater sensitivity towards no load capacitance to a higher f.
While I was recalling all my VCXO designs for pullability and modelling on Falstad's simulator, I took a quick google search and found
Maxim already had an excellent report on sensitivity for a 27 MHz.
Their test results, Xtal , layout and IC for a 14 pF rated load cap, the ideal caps IMHO would have been 22 pF, 24pF 1% NPO, but were never tested by Maxim. The did test in 2 pF increments however such as C1=C2 = 22 and 24 pF (with 1% NPO, I presume) were just +14, -17 ppm on either side of 27 MHz.
Although I cannot assume they chose a perfect Xtal 0 ppm error with 14.0 pF, 23 pF/2 equates to an equivalent load of 11.5 pF with 2.5 pF for parasitic pF, if we did. Maybe, I missed something (TL/DR)....
That equates to approximately 31 ppm per 2 pF/23pF (~10%) or 2.7 ppm per 1% load cap error at Vdd=3.1V
Normally no ground plane is used, under the Xtal + cap, Osc pads, but just a guard ring around them, so as not to add much stray capacitance error. However, their report gave no indication.