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critical path problem

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sevid

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hi,all
2 questions:
1:I want to know how to find out the critical path of a design,e.g. for a combinational circuit, an always block, or an FSM. and how to extract the critical path.
2:I want to do that with the help of Primetime.at first,partition the design into several timing path;then calculate the delay of each timing path,the path with the largest delay is the critical path.ok?

thanks in advance
sevid
 

Firstly use Design Compiler to synthesis your design, the tool will give you results such as critical path.
For your 2nd question, basically the longest timing path is the critical path. Primetime is a powerful tools to analyze the timing path. For you, the Design Compiler is enough.
 

hi,

inorder to use the PT we should complete the synthesis frist then we can analyze the path because the synthesis compiler will try to optimise the critical paths.
the critical path which u think at pre synthesis may not be the critical path after the synthesis.
so do the synthesis and the analyze the worst path using the PT is the good methodology to get the critical path.

regards,
Ramesh.S
 

you can use pt to see critical path delay information!!
 

thanks a lot
i know that you can optimize ur critical path with the help of DC or PT,the four basic methods are listed as follows:
select special elements of ur library between registers,
change ur setting of input_delay or output_delay to compress ur logic between registers,
group and ungroup commands between boundaries,
set_flatten or set_structure ur designs

Added after 20 seconds:

but for the first question i asked,what i really want to know is how to find out the critical path in my RTL codes and then optimize my codes pre-synthesis without the help of EDA tools.
pls tell us ur viewpoint and any help will be appreciated.
sevid
 

1.please synth your code first. and check your timing report.
 

sevid said:
but for the first question i asked,what i really want to know is how to find out the critical path in my RTL codes and then optimize my codes pre-synthesis without the help of EDA tools.
sevid

Generally, It is difficult to find out the critical path in your RTL codes if the logic is complex. Actually in design, we dont need to find out the critical path in your RTL code.
The popular way to optimized our code is lile following :
1. write code
2. synthsis
3. check the timing report
4. if violation, modify the code
5. resynthsis
....


I hope this will clear you doubt.

David
 

use dc or pt to generate the timing report
 

Hi ,

Intersting question .

When you do design you need to estimate what is your target frequency ?
One will say one path crtical bcos if you have too much of combinational logic which you unable close timing ....

1) when DC will say it is critical path one should analyze
- whether it is due to pure combinational from flop flop is crossing module boundaries then you can use flatten/grouping to do better optimization ...
But opmization works only if it violates in reasonable limit .
- If you have violation in with in one module then you have too much of combinational logic from flop 2 flop .... so you can see the RTL code and introduce some flops or pipes to do timing closure ....
- without doing any thing DC/PT ... one can estimate based on how may adders he is using beteen flop to flop and with given Freq you can check whether it meets or not ....


regards
yln
 

Hi all,


in order to estimate the critical path before u do synthesis follow the following steps .

1. u have to know the entire architecture of the design.
2. u have to know the how much combinational logic u r implementing (i.e u have to imagin the what logic synthesis tool will map for u t code).
3.how many clock domains r there without proper syncronisation mechanisam.
4.u have to know the basic gate delay(2 input basic nand gate).
5.is there any multy cycle paths which u have to take care while designing.

like this there r so many proble u have to know.may be it will help u .

regards,
rameshs
 

PT can indicate the critical path.
 

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