Critical path in SRAM

[vinod488]

critical path modeling of sram

Hi,
Anyone can tell what is critical path in SRAM.
What are conditions we have to take care for proper functioning.

 

[xreaver]

access time of sram read operation

well for a single port SRAM, the critical path includes the path from CLK generation to output generation. Usually READ operation is considered to be worst critical path.
The READ operation starts with input signal setup times with respect to CLK. and then the CLK generation, the internal CLK generation for latching all the input signals. Then, the address decoding part including ROW decoding and column decoding(for mux designs). followed by Wordline generation. The Wordline selecting the particular address or bitcell storage node. At the same time, the Sense signal generation to sense the differential voltage between bit and bitb lines for READ. The Wordline turns on, the bitlines discharge and the SenseAmp is enabled and a sufficient amount of differential voltage is achieved for a proper READ to happen. The senseamp output is then latched and given to the output.
So, a long process, but this is wat a critical path in SRAM is!
The Critical path should contain the blocks starting from CLK generation to input latching to address decoding to Wordline generation to bitcell block to Sense signal generation to Sense signal enabling to output latch. Basically determining your access time and cycle time! CK to OUTPUT is your access time usually...and CK TO OUTPUT + SETUP TIME is your cycle time usually...The critical path will contain both READ/Write operation circuits...and will calculate both. But always READ is considered to be the worst operation of the two...

 

[vinod488]

setup time read sram

hi,

Thanks for ur reply.

Canu u tell me the which material is best for Memories with access time and critical path calculations.


Regards,

 

[xreaver]

sram critical path

Rabey/Kang discusses about the memory blocks in detail and gives a good idea...but i think once you start doing a critical path, you will learn more with experience.
Just check the attachment - gives u some insight into RAM architectures and blocks

 

[pvvikas]

critical path sram

@xreaver,

I found this thread while searching for bitcell simulation. I am having a small problem in the same.
During reading from the cell, the voltage(VDD=1.2V) at BitLine(BL) is going to 1.27 which is higher than 1.2??!!
For testing, I have connected the precharge PMOS gate to WL(WordLine).

What could be the reason for this hike in the voltage when reading back a '1' from the bit cell?

Thanks
Vikas

Added after 5 hours 44 minutes:

@xreaver,
hey, never mind. I had not connected a cap load at bit line and bit line bar.

 

[gcreddy]

Critical path in the SRAM is activated when a logic 1 is read from the cell at the first row's last column. This constitutes the critical path because when the word line is asserted from the row decoder, it has to charge ALL the gates of the pass transistors preceding the final column before the final column's pass transistors are asserted high. Likewise, after this process, when a 1 is read from this cell, it has to charge all all the parasitic capacitors in the entire column before charging the read / write buffer input.

Likewise, there exists a critical for a write operation with certain riders which I do not remember precisely. You can figure it out by yourself if you think about the write operation on the previous lines.

Thank you.