elcielo
Full Member level 6
https://www.altera.com/servlet/down...vice_packs/quartus/dnl-q50-critical-issue.jsp
An issue has been discovered in Quartus® II software version 5.0. This issue can cause a small percentage of designs that use the ALTSYNCRAM megafuntion, under a particular set of conditions, to function differently than the user intended for CycloneTM, Cyclone II, Stratix®, Stratix II, and Stratix GX device families. No other device families are affected. This issue occurs in the Quartus II software across all operating systems (OS) and in the free Quartus II Web Edition software; Quartus II software versions 4.2 and earlier are not affected by this issue. This page is intended to inform you about the issue and to provide instructions to fix it. Altera has corrected this issue, and patches are now available for installation.
How Can this Issue Affect My Design?
How Can I Detect if this Issue Is Affecting My Current Design?
How Do I Fix this Issue?
How Can this Issue Affect My Design?
All platforms of Quartus II software version 5.0, including the free Web Edition, have an issue in the ALTSYNCRAM implementation such that the wren signal may be connected to Vcc instead of GND as the user intended. This issue occurs only when all of the following conditions occur:
The design targets a Cyclone, Cyclone II, Stratix, Stratix II, or Stratix GX device AND
ALTSYNCRAM implemented in simple dual-port mode (one read port and one write port) AND
Initial content of the memory is specified (from MIF or HEX file) AND
Write enable signal ("wren") is connected directly to GND AND
Clock enable signal ("enable") is not used AND
Write address stall signal ("wr_addressstall") is not used
How Can I Detect if this Issue Is Affecting My Current Design?
This issue will not show up in simulation and can only be detected in circuit. The RAM circuit will not act like a ROM even though you connected the write enable signal to GND. The initial data specified in the MIF or HEX file will get unintentionally overwritten.
How Do I Fix this Issue?
Selecting the ROM mode operation of ALTSYNCRAM will fix this problem and has the same effect as the designer intended by connecting the write enable signal directly to GND. Patches are also now available to fix this issue in all modes of ALTSYNCRAM operation. For each Quartus II software platform you can download a specific patch file that will fix only this issue.
This issue will also be fixed in service pack 1 due to release June 27, 2005. Service pack 1 will include other features and enhancements as well.
Please use the following tables to download the correct software patch for your specific installation. Table 1 is for subscription users and Table 2 is for Web Edition users.
An issue has been discovered in Quartus® II software version 5.0. This issue can cause a small percentage of designs that use the ALTSYNCRAM megafuntion, under a particular set of conditions, to function differently than the user intended for CycloneTM, Cyclone II, Stratix®, Stratix II, and Stratix GX device families. No other device families are affected. This issue occurs in the Quartus II software across all operating systems (OS) and in the free Quartus II Web Edition software; Quartus II software versions 4.2 and earlier are not affected by this issue. This page is intended to inform you about the issue and to provide instructions to fix it. Altera has corrected this issue, and patches are now available for installation.
How Can this Issue Affect My Design?
How Can I Detect if this Issue Is Affecting My Current Design?
How Do I Fix this Issue?
How Can this Issue Affect My Design?
All platforms of Quartus II software version 5.0, including the free Web Edition, have an issue in the ALTSYNCRAM implementation such that the wren signal may be connected to Vcc instead of GND as the user intended. This issue occurs only when all of the following conditions occur:
The design targets a Cyclone, Cyclone II, Stratix, Stratix II, or Stratix GX device AND
ALTSYNCRAM implemented in simple dual-port mode (one read port and one write port) AND
Initial content of the memory is specified (from MIF or HEX file) AND
Write enable signal ("wren") is connected directly to GND AND
Clock enable signal ("enable") is not used AND
Write address stall signal ("wr_addressstall") is not used
How Can I Detect if this Issue Is Affecting My Current Design?
This issue will not show up in simulation and can only be detected in circuit. The RAM circuit will not act like a ROM even though you connected the write enable signal to GND. The initial data specified in the MIF or HEX file will get unintentionally overwritten.
How Do I Fix this Issue?
Selecting the ROM mode operation of ALTSYNCRAM will fix this problem and has the same effect as the designer intended by connecting the write enable signal directly to GND. Patches are also now available to fix this issue in all modes of ALTSYNCRAM operation. For each Quartus II software platform you can download a specific patch file that will fix only this issue.
This issue will also be fixed in service pack 1 due to release June 27, 2005. Service pack 1 will include other features and enhancements as well.
Please use the following tables to download the correct software patch for your specific installation. Table 1 is for subscription users and Table 2 is for Web Edition users.