Creation of Dummy at the level of Layout

[plasma2000]

Hello, my friends.

I am actuelly drawing a layout containing some resistors and transistors beside which some dummys should be added.

Is it possible to draw the dummy myself? If yes, How many levels should I draw for MOS, Resistor, npn?

I have done a current souce. In the picture, some PMOS share the Drain and Source which are not connected to VDD.

I have heard that for a PMOS dummy, all terminals should be connected to VDD. And here in this case, shall I let it share the Drain or Source with his neighbor???

Finally, here I draw the 4 PMOS in "1221", Is it prefered to use commun centroide structure???

Thanks for your Help! Merci bcp!

 

[sambireddy]

yes u can draw the dummies yourself or u can use a pcell to make the total number of legs. for the case u have mentioned its better to interdigitate the transistors as 1212 and place one dummy on either side. u can share the drain of the dummy with the next transistor and connect the source to the vdd.

 

[pratyusha]

dummies are used to provide equal environment and during etching all the matched devices have to be etched similarly .

In mos dummies the dimension of the device must be same to the matched device .In dummy mos all the three terminals are connected to power pins i.e vdd , gnd . You can share the dummy drains with neighbours if they are connected to vdd.

Dummy ploy resistors are need not be of same dimension to the matched one. only poly strip is enough. Dummy nwell resistors need the same dimension to the matched one.

In matching first know what type of matching is needed. if it is minimal matching just place normally and route symmetrically . for moderate do interdigitied . for critical matching do the commoncentroid.

 

[plasma2000]

Dear pratyusha:

Do you know the percentage of mismatch of the 3 method for matching?

1,place normally and route symmetrically
2,do interdigitied
3,do commoncentroid

 

[fendy]

Dear Pratyusha,
I have some question for you:
1.Why does the MOS dummy need the same dimension to the mattached device ?As we all know,
"dummies are used to provide equal environment and during etching all the matched devices have to be etched similarly " If I have a dummy MOS who dimension different from the matched MOS, will the mismatch increase ?
2.Does the symmetrically mismatching less than commoncentroid's ?
3.Does the commoncentroid the same as crosee couple ?
THKs
BR

 

[pratyusha]

in practical , the layouts are not rectangular as we drawn. so the active region are not ending abruptly at the edge . It is diffusing and overlapping with the adjacent actives. so if we didn't maintain same dimensions this overlap may vary and cause mismatch.

crosscoupled is one type of commoncentroid arrangement.

i told for minimal matching just place devices close to each other and maintain routing symmentry.

Added after 45 minutes:


two types of matching are there . one is volatge matching and another is current matching

the degrre of mismatch is depends on the three sigma value given by the foundary.

for minimal matching : offset exceeds more than 10mV

for moderate matching : offset is less than 5mV or drain currents mismatch is less than 1%

critical matching : offset is less than 1mV or drain currents mismatch is 0.1%

 

[plasma2000]

pratyusha said:
In mos dummies the dimension of the device must be same to the matched device .In dummy mos all the three terminals are connected to power pins i.e vdd , gnd . You can share the dummy drains with neighbours if they are connected to vdd.
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In my case, the dummys' neighbours are not connncted to vdd r gnd. Shall I place the dummys a little far away from them??

 

[fendy]

Is the interdigitied better than symmetrically ?

 

[pratyusha]

In my case, the dummys' neighbours are not connncted to vdd r gnd. Shall I place the dummys a little far away from them??

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yes , u have to place individual mos device as dummy and maintain the same distance as matched devices. In layouts there is no rigid rules . we have to draw depending on the constraints. for example, area is main constraint. then there is a tradeoff between matching and area. sometimes i just use single poly strips as etch guards for the mos devices when there is no area for me. otherwise i will choose mos devices with minimum length . if there is more area then i wil go for the dummies with equal dimensions as matched one.
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interdigitied is one method where symmetry is in only one direction.
commoncentroid has symmetry in two directions.
[/b]

 

[plasma2000]

So here I should seperate the shared drain (or source) if I add 2 dummy MOS, or I should use a poly stripe.

And I could not let a dummy MOS be a little far away from the 4 desired MOS??

It's great, you help, thx!

 

[pph_cq]

I think poly strips is better than mos dummy. If you add dummy mos you have to tie it's drain,source,and gate to the drain of neighbour(mos 1), this will increase the loading of this net.