creating two diffrents clocks

[shay127]

i build a project that use two different clocks for two units. the main gool of it is to active unit 1 with clk1 and after unit 1 make its outpot to unit 2 i want to active unit 2 with clk2.
now the project work fine but i don't know how to make SDU for TB with two different clocks.
is that possible?

 

[KillaKem]

I don't really understand what you are trying to do, are you trying to derive one clock from another one? e.g you have a 20MHz clock and you are trying to derive a 5Hz clock from it so you can use the 20Mhz clock to power one component and the 5Hz clock to power another.If this is what you are trying to do you could design a module that takes the fast clock as an input and then uses a counter to count the number of clock cycles that have elapsed and then outputting a CLK pulse when the count reaches a user specified value of N.That output clk pulse will be your other clock.

 

[mrflibble]

better problem description plzkthxbye

 

[permute]

other than "SDU" it seems ok:

from what I can gather, he wants two gated clocks. when unit1 is active, clk1 is toggling. when unit1 finishes, and provides an output, clk1 stops toggling and clk2 begins toggling. (further states are not listed.) this can be done using the BUFGCTRL in xilinx, and a similar component in altera (IIRC). However, for simulation, there is apparently something called an SDU which is more difficult to write for this case. I'm not familiar with "SDU", nor did a google search for SDU+{eda,simulation} provide any clues to the meaning.

 

[mrflibble]

other than "SDU" it seems ok:

I found it a bit ambiguous, since I could take it to mean multiple things. But if you guessed it right and the OP got his answer, then problem solved.