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creating and instantiating *.nmc in a VHDL design

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souri98

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I checked the following link to make a hard macro (*.nmc).
But I do not know how to instantiate it in my design.

Could you please help me with a simple example?
Or if there is any tutorial on it?
 

TrickyDicky

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With these things, you usually have to create a component for it, and then add the attribute syn_black_box (or similar) and set it to true for that component. This tells the synthesisor to ignore it during synthesis and add it in at the fitter stage.
 

souri98

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Step 6 of that link is required? I mean creating a "symbol"? and would you please tell me how to use this attrib?

---------- Post added at 18:16 ---------- Previous post was at 18:07 ----------

Because writing :
attribute syn_black_box : boolean;
attribute syn_black_box of BEHAVE : architecture is true;
gives synthesis error. Also my macro is not recognized in "Design" window.
 

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