Creating a system that takes two 3-bit inputs and outputs a 4-bit number

Hello,

I have tried to do some research on my own and trying to implement this on Vivado for a class. My professor is horrible at teaching and I am a IT major and just trying to understand basic verilog but did not know it would be this hard. I am not strong on this subject so please be patient.

So far I have came up with a full adder but not sure how to implement the output on a 7 segment display. My verilog so far:


Is there anything I am missing or need to display it on a 7 segment display? I am really confused!

Hi,

There is no error description.
Did you test it or even simulate it?
I recommend to first do so.

Klaus

First, you've come the right place for hardware related questions.

Second, you need to swap your software hat for a hardware hat.

Going with your requirements

1. Lets focus on the module/entity
The 4 bit output is probably cout and sum concatenated together.


2. Lets focus on what a full adder is.
https://www.circuitstoday.com/half-adder-and-full-adder
Scroll down to logical representation of it. Furthermore see how it's chained together.
>>cout from one becomes cin to the other.

3. start with 1 bit full adder then scale it.

wesleytaylor said:

First, you've come the right place for hardware related questions.

Second, you need to swap your software hat for a hardware hat.

Going with your requirements

1. Lets focus on the module/entity
The 4 bit output is probably cout and sum concatenated together.

---

Code Verilog - [expand]
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module   full_adder(
    input cin,
    input [reg_size-1:0] in_a,
    input [reg_size-1:0] in_b,
    output [reg_size[B]-0[/B]:0] sum
    );
parameter reg_size = 3;
wire cout; // carry out
sum[4] = cout;

---

2. Lets focus on what a full adder is.
https://www.circuitstoday.com/half-adder-and-full-adder
Scroll down to logical representation of it. Furthermore see how it's chained together.
>>cout from one becomes cin to the other.

3. start with 1 bit full adder then scale it.

Click to expand...

Not sure why it was necessary to show a different version of the code with a combined {sum,cout} as sum[4:0] which by the way is wrong.
The OP wants 3-bit inputs and a 4-bit output, you are showing the carry is on the 5th bit. Besides they parameterized the width and if we stick with your code it would be shown as sum[reg_size] would select the cout bit.
------------------------------------------

Now the real inefficiency of the implementation has nothing to do with the functionality of the code, it has to do with synthesis implementation of what you've described.
This will result in two adders being implemented when only one adder should be implemented to create an optimal result.

If you think of binary math consider the equation 01+01 = 10. Now if you consider adding two 1's together generates a "carry" then use that to your advantage and write the addition as:
if we concatenate the cin to both the A & B inputs we can then add two 1's together (if cin is 1) and end up with a carry in for the adder (a 10). The x is a throwaway bit as we concatenated an extra bit to the end of the in_a and in_b vectors.

To generate the output for a BCD use the double dabble to convert the binary to BCD if you need more than a single digit of BCD. Use a case statement to convert the BCD values (or a single digit binary) value into the 7-segment enables (assuming the 7-seg is the type that doesn't have multiple digits and uses a serial protocol).