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CPU Core RTL Verification

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ravi123

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I want to do verification of CPU core.
I wanted to know if I am using systemC for verification. What could be the best methodology to verify different assembly instructions. If CPU core has pipelined architecture how to validate the output after each instruction in case of random simuations.
thanx
 

Wriiting Testtbenches which u can fing in this forum has some description how to verify a CPU
 

writtin testbench for ALU which is pipelined might be a very a very difficult process.. the best i suggest is verify each and every unit seperatly

is ur ALU unit Application specific or General purpose.. check givin values.. force them for random values and find the appropriate results.

try and let me know.. if its asyn ckts.. u have seperate tools for simulations

with regards,
 

You may read the paper at the link below:

**broken link removed**
 

Hi,
Hi just now we have finished testing one such processor!
This is what we followed
We are having MIPS like processor with single issue 16 hardware threads.
1. Basic instruction testing..
Here we did directed testing. Write small program to do some
arithmetic or logical operation and depending on result jump to
pass or fail location.
This method is used to test all arithmetic and logical instuctions
along with jump instructions.

2. Catche memory testing.
Generate catche miss conditions randomly.

3. Random testing.
Generate random assemply programs and run them both on rtl and ISS written
in systemC compare register dumps at each instruction execution. At the end of
simulation compare the data memories.

4. Multithreading testing.

5. Interrupt and exception handling testing.

Hope this helps.
 

if all units are functional correct ,at least,u can make top testbench ,read instructions from ROM,and test ur cpu core.
 

Hi, ravi123,

I append some points to nand_gates.

(1) SystemC could build the behavioral model of your processor. Especialy for the arithmetic of the Fixed-Point Unit and Float-Point Unit.

(2) Assembly codes are in integrated with scripts and verficaiton env. Such as shell, perl.

(3) IEU of your processor is very important unit. You should make ensure the FSM of IEU is good.

(4) You might build FIFO architecture behavioral monitors for your pipelined instructions architecture. Certainly, there should be not disorder instructions.

Hope to help.

Good Lcuk!
 

I recommend to use Verisity's Verification Tools. It has a property specification language called E-language which is suitable to describe large designs like CPU in a behavioral model. Also you can have your RTL model of CPU. the equivalence checking of them will be great.
You can find some articles about E-language and Verisity methodology to do functional verification in EDAboard.

Regards
KH
 

for instructions set, must think about all boundary case,

Added after 6 minutes:

a simulitor is good for your verification,
you can compare the response between your cpu and simulitor
 

Hi,
1. I am using ISS for random Simulation.
2. all instructions and addressing modes verified with directed testcases.

But I am still not clear how to verify the pipeline in the processor.
Do u guys have any idea on this.

thanx
 

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