CPLD vs FPGA verilog

[digi001]

I have done a few designs on FPGAs in Verilog, but need to now write some HDL for a CPLD.

The CPLD happens to be on a Fiber Optic board I want to use for some development work so this is why I am using it.

Anything I should keep in mind writing HDL for a CPLD vs FPGA? This will be some pretty basic code. Should it synthesize roughly the same?