[SOLVED] CPLD interface help required

[shashy.br]

Dear all,


I am planning to use a CPLD for controlling the attenuation value of the Digital attenuators used for my RF synthesize application as shown in the figure.

the plan is to provide the command from the RS422 interface available externally to the CPLD in order to change the attenuation value of individual digital attenuators.

Do i need to provide a clock to the CPLD for this operation ?

i am new to the CPLD , please share your knowledge

https://obrazki.elektroda.pl/1594815400_1353561020.jpg

 

[FvM]

Do i need to provide a clock to the CPLD for this operation ?

Absolutely. Every UART needs a clock to sample the input data. There are many previous threads about UART design in programmable logic, e.g. https://www.edaboard.com/threads/137269/

 

[shashy.br]

Thanks for the quick reply

 

[shashy.br]

Also i needed to know if only one clock is sufficient for the CPLD ?

I am planning to use a 14.75MHz oscillator as the clock source for the CPLD.

do i need to consider any other parameters for the design implementation.

 

[FvM]

One clock should be pretty sufficient. As a special advantage of the CPLD UART, you're not necessarily restricted to standard UART crystal frequencies, because you can use uncommon oversampling ratios. I'm e.g. operating a 115k UART with a 6 MHz clock by using an OS factor of 13 instead of 16.

 

[shashy.br]

Thank you for the clarification...!!!

- - - Updated - - -

i will elaborate my quiery.

i am using XC2C32A Coolrunner II CPLD for my application.

the datasheet says that the clock division is possible such as /2 , /4 ,/8 and /16.

The baud rate for my communication is 115.2 Kbps , i couldnt select the Oscillator needed for this application.

can u please help me in this regard. ?

i have selected the maximum clock frequency possible as 1.8432 MHz ( 115.2 Kbps * 16) , is this right?

 

[FvM]

Baud rate generation hasn't much to do with the clock division features of the CPLD. You'll want to use one system clock of suitable speed and generate clock enable signals of lower frequency at the UART baud rate respectively baud*OSR (oversampling rate). These clock enables aren't clocks.

It should be possibe to implement a well considered design in 32 macro cells. Providing 64 macro cells would ease things a lot.

 

[shashy.br]

Thanks a lot for the help... also i needed one more clarification .

does implementing a UART core inside the CPLD depend on the number of macrocells ?

if so which CPLD should i choose for the UART core to be placed inside it to control the I/O lines.?

i selected a XC2C64A coolrunner IC and simulated it using Xilinx to verify the feasibility of using it ...and the Xilinx mentioned that it contains insufficient number of macrocells...!!!

 

[FvM]

I was talking about a "well-considered" design for small CPLDs thoughtfully. An arbitrary UART core from the internet won't fit most likely. Functionality has to be minimized to the bare necessities. Data decoding to select both output latches must be minimized, too. If you don't have a feeling how HDL code is converted to hardware, it may me better to sketch the intended hardware logic first.

 

[shashy.br]

Thanks for the reply,

The coding was done for the basic UART interface for my application and simulated using a XPLA series CPLD with 256 macrocells

the design utilized 36% of the Macrocells hence i went ahead with XCR3256XL-10TQ144I CPLD .