cpld for pci bus interfacing

[priyaphule]

i want to use cpld for interface control lines of cpu ie between the back end bus and the local bus of pci controller

how i should achive the timing constrains between the cpu back end bus and pci local bus

 

[xofun]

hi,
you know i am a beginner as u. I think u can use synopsys or symplify or other tools to add constrains.Of course,there r many IP core and info aviliable at internet,and try to search google to find some. U can alse find it with search in this site,for it is not a new question.

BEST REGARDS

 

[Renjith]

go thrg the specs of the bck end bus protocols and pci controller. use the constrain editor of xilinx ise to put the timing constraints.

 

[dainis]

http://www.ben.com/minipci/