cpld for pci bus interfacing

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priyaphule

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i want to use cpld for interface control lines of cpu ie between the back end bus and the local bus of pci controller

how i should achive the timing constrains between the cpu back end bus and pci local bus
 

hi,
you know i am a beginner as u. I think u can use synopsys or symplify or other tools to add constrains.Of course,there r many IP core and info aviliable at internet,and try to search google to find some. U can alse find it with search in this site,for it is not a new question.

BEST REGARDS
 

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    priyaphule

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go thrg the specs of the bck end bus protocols and pci controller. use the constrain editor of xilinx ise to put the timing constraints.
 

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