cpld clock crystal circuit
Hi,
I am also new to CPLDs and ask a question similar to above.
I have just bought a CPLD kit that has an Altera EPM7128S CPLD on it and LEDs, buttons, RS-232
interface, 7-segemnt displays. I have attached a schematic of this kit.
Also, there is a 47B47 microcontroller on the board that is said to supply the clock for CPLD.
The clock frequency is controlled by a potentiometer connected to analog input of the
microcontroller. Simply, microcontroller gives a clock to CPLD that depends on the
potentiometer's value. All are OK.
But since I am also new to CPLD, and I have looked at the datasheet of the CPLD, there are 4 pins
that I want to understand.
1. INPUT/GCLK1
2. INPUT/OE1
3. INPUT/OE2/GCLK2
4. INPUT/~GCLR
*I think, I've to give logic 1 to OE1 and OE2 (to enable output, whatever circuit I build), is it
correct?
*What is the functionality of INPUT/~GCLR
*From the replies to this posts, I understand that I can set any I/O pin of CPLD as a clk pin.
But why is there a INPUT/GCLK1 pin? It is also marked in the datasheet?
Thanks for reading this long question list
Regards