CPLD board pin problems (Xilinx Webpack 7.1 and VHDL)

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revolt

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Hi,

I designed a little CPLD board (xc9536) and now I want to check if everything is fine. So I started to try to toggle pins. That were the trouble began. I use Xilinx Webpack 7.1i / VHDL and want to assign the pins Vccio or Gnd, like this

LED0<='0';
LED1<='1';

But the both pins have a high level. When I use another pin as input and do this:

LED0<=Button;
LED1<=not Button;

the voltage at the LED0/1 pins is correct.

Has somebody made the same experiences?

regards revolt
 

CPLD pin problem

okay, problem is solved.

In the Webpack the option "Create Programmable GND Pins on Unused I/O" was enabled. After disabling everything works fine.

regards
revolt
 

Re: CPLD pin problem

Should you use unquoted values instead?

LED0<='0';
LED1<='1';

'0' is equivalent to ASCII value '0' (0x30 or 00110000) and '1' (0x31 or 00110001).

This would probably work only because the LSB is taken (since LED0 and LED1 are 1-bit).


Better use

LED0<=1'b0;
LED1<=1'b1;
 

CPLD pin problem

LED0 is a std_logic type.
I always use <='0' for std_logic and never had a problem with it.

Is your code for verilog? in my VHDL it doesn't work.
 

Re: CPLD pin problem

how u knew that both of led0/1 are high?

did u simulate ur code and it show them high?or u checked it on the board?
 

CPLD pin problem

I checked it on the board
 

Re: CPLD pin problem

revolt said:
LED0 is a std_logic type.
I always use <='0' for std_logic and never had a problem with it.
Is your code for verilog? in my VHDL it doesn't work.
Click to expand...
Hi!
The notation LED0<=1'b0; is exactly verilog. I was also surprised by your <='0' code. I have never used it.
But sometimes I use a notation like LED0<=0; and it works too. I think it might depend on compiller. I mean, does it accept that or not.
 

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