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CPL BIT in oregano mc8051

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irun2

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Have anyone used the oregano mc8051 core? Recently I have a project related to microcontroller, and I find mc8051 meets my requirements. The functional verification with modelsim is good, but when I synthesis it with altera cynclone 2 device, all seems fine but the CPL bit, say CPL P3.1, P3.1 just holds it value the first time it's set! Would it be a bug of this ip? Current version of the design files is 1.5.
I've tried to find the cause but without luck. I just followed the instructions depicted in mc8051_cyclone_nios_designflow.pdf to setup a project in QuartusII, don't know if it needs some more work to do beside that
 

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