Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Coverage for interface signals in UVM

Status
Not open for further replies.

Yankie

Newbie level 4
Joined
Dec 12, 2012
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,345
Hi,

I have a question regarding coverage in UVM monitor.

Presently, I have a base_test that extends from uvm_test. It directly creates the UVM monitor. The monitor reads the signals on the interface and pushes the read data in an internal mailbox. It does not have a TLM port.

I want to cover the signals present on the rx_if_0 interface. The below code does not seem to work.
Also, following changes did not work:
1) Omitting the virtual keyword from covergroup i.e covergroup fc_cov() with function sample (rx_intf rx_rcv_if);
2) Passing the interface handle while creating the covergroup i.e fc_cov cg= new(rx_if_0);
3) Omitting the instance name cg i.e fc_cov = new();


What is the best solution for covering the signals of rx_if_0 interface? I want to sample the signals at every posedge of clock.
Appreciate your help !

Thanks,
Kaveri


CODE:


My_monitor.sv :

covergroup fc_cov() with function sample (virtual rx_intf rx_rcv_if);
coverpoint rx_rcv_if.pkt_id;
endgroup

class my_monitor extends uvm_monitor;

virtual fencer_rx_if_bus.rcv rx_if_0;

virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);

if(!uvm_config_db#(virtual rx_intf)::get(this, "", "mon_rx_if" , this.rx_if_0))
`uvm_fatal(. . . . .);

fc_cov cg= new();
endfunction

virtual function void start_of_simulation_phase(uvm_phase phase);
super.start_of_simulation_phase(phase);
cg.sample(rx_if_0);
endfunction
endclass



Base_test_include.sv

class base_test extends uvm_test;
`uvm_component_utils(fencer_base_test)
my_monitor mon;

function new(string name="test", uvm_component parent);
super.new(name, parent);
endfunction

virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
mon = my_monitor::type_id::create("mon", this);
uvm_config_db#(my_monitor)::set(this, "*", "mon", mon);
uvm_config_db#(virtual fencer_rx_if_bus)::set(uvm_root::get(), "*", "mon_rx_if", top.rx_if_0);

endfunction
endclass
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top