Coupled inductor sepic article is inaccurate?

[treez]

Hello,
On the top left of the 4th page of this article the reader is recommended to add a heavy RC snubber in order to mitigate the low-ish frequency ringing seen in the uncoupled inductor sepic.............this is bad advice..do you agree?

The only reason you would suffer such a bad ringing (in an uncoupled inductor sepic) is if your sepic converter's feedback loop crossover frequency was too near the resonant frequency of the sepic capacitor and the two uncoupled sepic inductors. You should not use a snubber, but instead should arrange it that the feedback loop crossover frequency is not near the aforementioned resonant frequency.

https://www.ti.com/lit/an/slyt411/slyt411.pdf

 

[FvM]

I believe that the author observed unstable behaviour. No feedback frequency characteristics are shown, so it's not clear if stability could be achieved otherwise. A more practical consequence would be not to use uncoupled SEPIC inductors with a current mode controller.

 

[treez]

Uncoupled sepic inductors can be used as long as the L,L,C ringing frequency is well above the feedback loop crossover frequency. Also, the C must be large enough that it provides low impedance to the switching waveform , obviously at the switching frequency....the question would be, how low?

 

[FvM]

Uncoupled sepic inductors can be used as long as the L,L,C ringing frequency is well above the feedback loop crossover frequency.

If you calculate the resonance frequeny, you understand why this isn't a good option.

 

[treez]

Actually, further research has found that the feedback loop crossover frequency has little to do with the instability...
https://www.edaboard.com/threads/298786/

The instability appears to be something to do with current mode sepics which have duty cycle above 50%.

 

[mtwieg]

I've seen such damping (not snubbing) circuits used in SEPIC and Cuk converters before. The purpose is basically smooth out the transfer function to eliminate sharp peaks in the magnitude response and steep drops in phase response, both of which make instability more likely.

 

[treez]

The following article states how adding leakage inductance to a coupled inductor sepic converter can reduce the RMS inductor currents…

Do you agree that the article is like telling people to get to the surface to breath when diving, without telling people that they must rise slowly in order to avoid the bends…in other words, no information is better than “not enough”?

**broken link removed**

However, “A little knowledge is dangerous” and the article fails to mention that adding leakage alone is not enough, and indeed can cause more problems if not done properly.
-if significant leakage is added, then there is a danger that the leakage inductance and the sepic capacitor will cause severe ringing in the inductor current. Such ringing will need a RC snubber to be placed across the sepic capacitor. The R(snubber) should be sized as per SQRT{L(leakage)/C(sepic)}.
The C(sepic) should then be sized as 1/{2*pi*f*R(snub)}
..where “f” is the resonant frequency of C(sepic) and L(leakage).

This particular ringing only occurs if the duty cycle exceeds 50%.
This ringing is related to the feedback loop, and does not occur if the sepic is run “openloop” (with a fixed duty cycle). If the L,C ringing frequency is too near the feedback loop frequency,then that’s what sets off this ringing.

The power rating of the R(snubber) depends on the amount of transient activity on the output…..with much transient activity, this resistor will need a higher power rating.

The sepic capacitor shown in the schematic of the above artcle is too small, and should be sized at 18uF, which ensures that the ripple voltage on the C(sepic) is less than 5% of the input voltage.

 

[mtwieg]

-if significant leakage is added, then there is a danger that the leakage inductance and the sepic capacitor will cause severe ringing in the inductor current.

I don't think so. The resonant frequency formed with the leakage inductance should be well below the switching frequency, and thus it shouldn't be excited by switching. However, that resonance will then appear in the SEPIC control transfer function. You can deal with it by setting the cutoff frequency far below that, or by damping the resonance with a RC network, which will allow a somewhat higher fc.

This particular ringing only occurs if the duty cycle exceeds 50%.

Why do you think this is the case?

This ringing is related to the feedback loop, and does not occur if the sepic is run “openloop” (with a fixed duty cycle). If the L,C ringing frequency is too near the feedback loop frequency,then that’s what sets off this ringing.

Then the lesson is to do a good job designing the feedback loop, same as with any other converter. The article isn't about control, it's about ripple and efficiency, so don't be surprised that it doesn't discuss those issues in depth.

 

[FvM]

While the paper cited in post #1 is discussing meaningful design setups with real parts (uncoupled inductors versus a coupled inductor with typical coupling), the post #7 paper is confronting almost theoretical constructs, an unrealistic low and unusual high leakage inductance.

I don't see why we should discuss it as long as we are targetting to real designs.


A discussion about pro and cons of different coupling factors in a realistic range can be found in this previous thread https://www.edaboard.com/threads/250056/

To address some special points

The resonant frequency formed with the leakage inductance should be well below the switching frequency, and thus it shouldn't be excited by switching.

The resonance would be in fact in the switching frequency range for the (unrealistic) assumptions of the Powerpulse article.

However, that resonance will then appear in the SEPIC control transfer function. You can deal with it by setting the cutoff frequency far below that, or by damping the resonance with a RC network, which will allow a somewhat higher fc.

The point has been previously addressed in this and a parallel thread. https://www.edaboard.com/threads/299086/

1. You won't do that, because the low control reaction action isn't acceptable.
2. It won't stop the oscillations, because they are brought up in the current mode feedback loop. The instability mechanism is similar to the usual subharmonics without slope compensation, which explains the magical 0.5 duty cycle limit.

But in all configurations I have seen up to now, permanent oscillations could be found only with uncoupled or very loosely coupled inductors, apparently due to the higher resonance Q. Thus I concluded: don't use current mode with uncoupled SEPIC (and duty cycle >= 0.5 according to treez).

 

[treez]

Speaking first of the situation when L and C resonate somewhat below the switching frequency (in either uncoupled sepic or coupled sepic with much L(leak):

mtwieg, are you doubting that this L,C oscillation occurs?..(ie when L,C resonance freq is well below the f(sw))......you can see from presented sims that this oscillation always occurs in any sepic, whether current mode, or constant off time mode, whether DCM or CCM.............the only time it does NOT occur is

1..when duty cycle <0.5
2..when it is snubbed out by suitable RC across the sepic capacitor
3..In openloop sepic's
4...In voltage mode BUT only when you set the inner current loop max current cut off high enough not to invoke the start of oscillations
(the attached shows a voltage mode sepic (uncoupled) which doesn't ring...but if you set the source overcurrent lower then it does ring......this feature virtually invalidates VM sepic's ability NOT to ring, because it only doesn't ring when the source current limit is set too high. (the simulation shows the voltage mode sepic with uncoupled, and d>0.5, and no snubber, and a ridiculously high source current limit)

Does anybody out there agree with me that the undocumented features of the sepic converter need documenting?.....how about ti.com pick all this up, since on their website they offer about 100 sepic reference designs...or any other semico.


The following thread contains some of the proof simulations of my words...
https://www.edaboard.com/threads/298786/

 

[FvM]

Even in voltage mode, the unfortunate ring still happens...as per in the sim of this thread.

I won't say this can't happen. But the said simulation Sepic 5-15v VMode.txt is not implementing voltage mode. There's still a current feedback over node "cs". So the simulation doesn't prove anything.

My motivation to dive into the circuit details is slowly fading... I have no open questions presently.

 

[treez]

Surely it is voltage mode, the cs pin is just receiving a ramp from the chips oscillator?
...the comparator is just an overcurrent comparator, which doesn't operate when the currentis are within normal operating range

My motivation to dive into the circuit details is slowly fading

I appreciate if you don't use sepics much you mighnt be interested to the degree concerned..........but the sepic is a wonderfully cheap way of getting
1...cheap universal converter which can handle various loads, with vout above or below vin
2....doesnt need custom wound magnetics
3....doesn't need a flyback snubber
4.....has short circuit protection
5...can use a cheap low side fet driver type CM controller

And looking at the amount of sepic reference designs on ti.cm site, itisa worthwhile converter, I am sure you agree. see "reference designs"...

https://www.ti.com/product/tps40210

 

[FvM]

O.K., you are right the current sense is only active during start-up. The voltage feedback settings are almost damping the SEPIC series resonance, but it's probably unsuitable slow. At first sight, it looks like you can get an instable or at least ringing voltage loop response by the series resonance as well. The question is if it can be cancelled by well considered loop design, but this is probably not simple and would require exact loop gain analysis.

I don't believe that the duty cycle plays the same role regarding voltage loop stability as for current mode.

 

[treez]

I don't believe that the duty cycle plays the same role regarding voltage loop stability as for current mode.

..I believe you are contrasting Voltage mode and current mode sepics and considering there willingness to ring badly.
The voltage mode sepic is strangely free from the ringing..........this is something that is in the twilight zone...that zone of info that hasn't yet emerged from the depths of university depts.

 

[mtwieg]

The whole instability at D>0.5 is interesting, but I believe your misinterpreting your simulations. It's not a form of subharmonic oscillation, but there is something interesting that happens to the SEPIC at D>0.5... It's hard to explain, but if you go through the actual derivation of the transfer function it will reveal itself.

 

[treez]

according to Dr Ray Ridley, and other eminences, the transfer function for the sepic has never been worked out.

 

[mtwieg]

according to Dr Ray Ridley, and other eminences, the transfer function for the sepic has never been worked out.

Absurd, I've seen it documented from many sources and I've derived it myself (at least for the CCM case). I'm certain I've seen it explained in Ridley articles as well. There's no black magic to it.

 

[treez]

Absurd, I've seen it documented from many sources and I've derived it myself (at least for the CCM case). I'm certain I've seen it explained in Ridley articles as well. There's no black magic to it.

**broken link removed**
..please see page 16,centre , bottom, ...

AC Analysis of the Sepic Converter
You won’t find a complete analysis of
the Sepic converter anywhere in printed
literature.

The above article states how the sepic is very sensitive to changes in the parasitic circuit resistances...the loop transfer function changes greatly with only small changes in parasitic resistances.
This is bad news , because for some components, eg ceramic capacitors, the esr is not really known, and also, even if it is known, the tolerance range of it certainly is not known.

I'd say being able to calculate fully and properly the small signal loop transfer function of the sepic was obviously useful, but realistically, even Dr Ridley states that such calculation involves a "prodigious amount of work".......and in all that typing of numbers into Mathcad, can anybody be sure that they don't do a typo?....I think not.

Realistically, if doing a sepic, then really its better if its for a really benign converter like a constant loaded led driver.....where a "geek" sense of analog electronics will help assert stability.
Where any kind of certainty about gain and phase margin is needed for the sepic, then I would say a measurement of gain and phase margin with a frequency analyser was a necessity...and with the AP300, this only takes 5 minutes.

Supposing the bode plots are gotten by calculation, and also by AP300 measurement......then suppose the results differ....-which one would we believe?...we'd believe the AP300 measurement every time..and this kind of makes it a less valid use of engineering time to actually do the calculation..even if you do do it five times,so as to ascertain that there were no typos into Mathcad.

 

[mtwieg]

The above article states how the sepic is very sensitive to changes in the parasitic circuit resistances...the loop transfer function changes greatly with only small changes in parasitic resistances.
This is bad news , because for some components, eg ceramic capacitors, the esr is not really known, and also, even if it is known, the tolerance range of it certainly is not known.

So what Ridley is saying is that making accurate models of the SEPIC with all parasitics included is infeasible, and I can agree with that. But it is perfectly feasible to derive models which are instructive to designers, and can reveal the explanations for strange phenomenon such as yours.

I'd say being able to calculate fully and properly the small signal loop transfer function of the sepic was obviously useful, but realistically, even Dr Ridley states that such calculation involves a "prodigious amount of work".......and in all that typing of numbers into Mathcad, can anybody be sure that they don't do a typo?....I think not.

Depends on how exactly you want to model things. Accounting for ESR in the inductors and capacitors would probably not be too difficult, throwing in parasitic capacitances and inductances and source impedance would be quite challenging though (since they actually cause the size of your state matrix to grow). But such a deep analysis is not necessary to explain what you're seeing.

Realistically, if doing a sepic, then really its better if its for a really benign converter like a constant loaded led driver.....where a "geek" sense of analog electronics will help assert stability.
Where any kind of certainty about gain and phase margin is needed for the sepic, then I would say a measurement of gain and phase margin with a frequency analyser was a necessity...and with the AP300, this only takes 5 minutes.

Of course you always measure the TF at the end, but when you run into something like what you're seeing (a bifurcation in the transfer function), then crude measurements and simulations aren't going to help explain that much.

 

[treez]

Thanks,
Incidentally, I have written a document stating why the ti.com article below is rather wide of the mark, in its claim about the usefulness of loosely coupled sepic inductors.

Article concerning loosely coupled sepic inductors:
**broken link removed**

Attched is the document, as well as the LTspice simulations which prove what my document says is correct....they are the simulations of the sepic converters discussed in the ti.com article (both loosely coupled sepic, and tightly coupled sepic)