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Basically a good suggestion. But would need 64kx64 respectively 512 kByte of ROM. You'll have serious difficulties to meet the 266 MHz requirement.
The other suggestion is one of many possible sequential solutions. It's promising low resource usage, but only moderate speed. Unlike a fully parallel combinational design, it can't be pipelined without multiplying the resource count. It's unsuitable for high speed.
This is one of those problems that the engineering mentality likes to take on. It looks like it ought to have a quick and easy solution. Just a little more thinking outside the box should do it...
I'm learning new terminology from this discussion. Brainstorming is good.